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authorEric Biederman <ebiederm@xmission.com>2004-11-04 11:04:33 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-04 11:04:33 +0000
commit018d8dd60f2cc0c82faac0ee2657daa163dd43e7 (patch)
tree528de120d262a9df05ce8b6119f593c85fa6b809 /src/mainboard
parent4403f6082372d069e3cabe0918d9af5f9c1dccf6 (diff)
downloadcoreboot-018d8dd60f2cc0c82faac0ee2657daa163dd43e7.tar.xz
- Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/Iwill/DK8S2/Config.lb162
-rw-r--r--src/mainboard/Iwill/DK8S2/auto.c59
-rw-r--r--src/mainboard/Iwill/DK8S2/chip.h2
-rw-r--r--src/mainboard/Iwill/DK8S2/cmos.layout4
-rw-r--r--src/mainboard/Iwill/DK8S2/mainboard.c9
-rw-r--r--src/mainboard/Iwill/DK8S2/mptable.c30
-rw-r--r--src/mainboard/Iwill/DK8X/Config.lb161
-rw-r--r--src/mainboard/Iwill/DK8X/auto.c138
-rw-r--r--src/mainboard/Iwill/DK8X/chip.h4
-rw-r--r--src/mainboard/Iwill/DK8X/cmos.layout29
-rw-r--r--src/mainboard/Iwill/DK8X/mainboard.c7
-rw-r--r--src/mainboard/Iwill/DK8X/mptable.c30
-rw-r--r--src/mainboard/amd/quartet/Config.lb16
-rw-r--r--src/mainboard/amd/quartet/auto.c49
-rw-r--r--src/mainboard/amd/quartet/chip.h2
-rw-r--r--src/mainboard/amd/quartet/mainboard.c7
-rw-r--r--src/mainboard/amd/quartet/mptable.c26
-rw-r--r--src/mainboard/amd/serenade/Config.lb24
-rw-r--r--src/mainboard/amd/serenade/auto.c50
-rw-r--r--src/mainboard/amd/serenade/chip.h2
-rw-r--r--src/mainboard/amd/serenade/mainboard.c7
-rw-r--r--src/mainboard/amd/serenade/mptable.c24
-rw-r--r--src/mainboard/amd/solo/Config.lb16
-rw-r--r--src/mainboard/amd/solo/mainboard.c24
-rw-r--r--src/mainboard/arima/hdama/Config.lb14
-rw-r--r--src/mainboard/arima/hdama/cmos.layout2
-rw-r--r--src/mainboard/arima/hdama/mainboard.c307
-rw-r--r--src/mainboard/densitron/dpx114/Config.lb172
-rw-r--r--src/mainboard/densitron/dpx114/auto.c38
-rw-r--r--src/mainboard/densitron/dpx114/chip.h2
-rw-r--r--src/mainboard/densitron/dpx114/failover.c37
-rw-r--r--src/mainboard/densitron/dpx114/mainboard.c30
-rw-r--r--src/mainboard/digitallogic/adl855pc/Config.lb129
-rw-r--r--src/mainboard/digitallogic/adl855pc/auto.c25
-rw-r--r--src/mainboard/digitallogic/adl855pc/chip.h2
-rw-r--r--src/mainboard/digitallogic/adl855pc/failover.c37
-rw-r--r--src/mainboard/digitallogic/adl855pc/mainboard.c30
-rw-r--r--src/mainboard/emulation/qemu-i386/auto.c2
-rw-r--r--src/mainboard/emulation/qemu-i386/mainboard.c27
-rw-r--r--src/mainboard/ibm/e325/Config.lb174
-rw-r--r--src/mainboard/ibm/e325/Options.lb4
-rw-r--r--src/mainboard/ibm/e325/auto.c46
-rw-r--r--src/mainboard/ibm/e325/chip.h2
-rw-r--r--src/mainboard/ibm/e325/mainboard.c7
-rw-r--r--src/mainboard/ibm/e325/mptable.c26
-rw-r--r--src/mainboard/newisys/khepri/Config.lb174
-rw-r--r--src/mainboard/newisys/khepri/auto.c47
-rw-r--r--src/mainboard/newisys/khepri/chip.h2
-rw-r--r--src/mainboard/newisys/khepri/mainboard.c7
-rw-r--r--src/mainboard/newisys/khepri/mptable.c25
-rw-r--r--src/mainboard/technologic/ts5300/Config.lb19
-rw-r--r--src/mainboard/technologic/ts5300/mainboard.c28
-rw-r--r--src/mainboard/tyan/s2735/mainboard.c26
-rw-r--r--src/mainboard/tyan/s2850/mainboard.c107
-rw-r--r--src/mainboard/tyan/s2880/mainboard.c107
-rw-r--r--src/mainboard/tyan/s2881/mainboard.c107
-rw-r--r--src/mainboard/tyan/s2882/auto.c5
-rw-r--r--src/mainboard/tyan/s2882/mainboard.c107
-rw-r--r--src/mainboard/tyan/s2885/mainboard.c107
-rw-r--r--src/mainboard/tyan/s4880/auto.c2
-rw-r--r--src/mainboard/tyan/s4880/mainboard.c107
-rw-r--r--src/mainboard/tyan/s4882/mainboard.c108
-rw-r--r--src/mainboard/via/epia-m/Config.lb171
-rw-r--r--src/mainboard/via/epia-m/auto.c27
-rw-r--r--src/mainboard/via/epia-m/chip.h2
-rw-r--r--src/mainboard/via/epia-m/failover.c37
-rw-r--r--src/mainboard/via/epia-m/mainboard.c35
-rw-r--r--src/mainboard/via/epia/Config.lb34
-rw-r--r--src/mainboard/via/epia/auto.c13
-rw-r--r--src/mainboard/via/epia/failover.c37
-rw-r--r--src/mainboard/via/epia/mainboard.c28
71 files changed, 768 insertions, 2696 deletions
diff --git a/src/mainboard/Iwill/DK8S2/Config.lb b/src/mainboard/Iwill/DK8S2/Config.lb
index 47400f8559..c28b8d3ca7 100644
--- a/src/mainboard/Iwill/DK8S2/Config.lb
+++ b/src/mainboard/Iwill/DK8S2/Config.lb
@@ -1,110 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-#default MAINBOARD_PART_NUMBER="HDAMA"
-#default MAINBOARD_VENDOR="ARIMA"
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -123,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -145,15 +37,12 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
-#cpu k8 end
##
## Build the objects we have code for in this directory.
##
-#object mainboard.o
driver mainboard.o
-#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@@ -164,41 +53,41 @@ dir /drivers/ati/ragexl
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -210,11 +99,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-mainboardinit cpu/k8/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -232,9 +116,12 @@ end
##
## Setup RAM
##
-mainboardinit cpu/k8/enable_mmx_sse.inc
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -242,6 +129,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
dir /pc80
config chip.h
+# config for arima/hdama
chip northbridge/amd/amdk8
device pci_domain 0 on
device pci 18.0 on # LDT 0
@@ -330,9 +218,3 @@ chip northbridge/amd/amdk8
end
end
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-
diff --git a/src/mainboard/Iwill/DK8S2/auto.c b/src/mainboard/Iwill/DK8S2/auto.c
index 6761646be1..9b40059e43 100644
--- a/src/mainboard/Iwill/DK8S2/auto.c
+++ b/src/mainboard/Iwill/DK8S2/auto.c
@@ -2,10 +2,10 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
-#include <cpu/p6/apic.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -14,19 +14,21 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
- set_bios_reset();
+ set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
@@ -40,6 +42,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -68,7 +74,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
/* Routing Table Node i
*
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
+ * i: 0, 1, 2, 3, 4, 5, 6, 7
*
* [ 0: 3] Request Route
* [0] Route to this node
@@ -124,12 +130,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@@ -154,32 +156,39 @@ static void main(void)
},
#endif
};
+
int needs_reset;
-
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
-
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
-
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ /* Setup the console */
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
-
+
#if 0
print_pci_devices();
#endif
diff --git a/src/mainboard/Iwill/DK8S2/chip.h b/src/mainboard/Iwill/DK8S2/chip.h
index 0e961fd0e7..402cd5e6d2 100644
--- a/src/mainboard/Iwill/DK8S2/chip.h
+++ b/src/mainboard/Iwill/DK8S2/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_Iwill_DK8S2_control;
+extern struct chip_operations mainboard_Iwill_DK8S2_ops;
struct mainboard_Iwill_DK8S2_config {
int nothing;
diff --git a/src/mainboard/Iwill/DK8S2/cmos.layout b/src/mainboard/Iwill/DK8S2/cmos.layout
index 4a92876b07..f5325d15e8 100644
--- a/src/mainboard/Iwill/DK8S2/cmos.layout
+++ b/src/mainboard/Iwill/DK8S2/cmos.layout
@@ -73,6 +73,4 @@ enumerations
checksums
-checksum 392 1007 1008
-
-
+checksum 392 983 984
diff --git a/src/mainboard/Iwill/DK8S2/mainboard.c b/src/mainboard/Iwill/DK8S2/mainboard.c
index 0db6bd043a..465eb3d6d0 100644
--- a/src/mainboard/Iwill/DK8S2/mainboard.c
+++ b/src/mainboard/Iwill/DK8S2/mainboard.c
@@ -3,14 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-
-struct chip_operations mainboard_Iwill_DK8S2_control = {
- .enumerate = enumerate,
- .name = "Iwill DK8S2 mainboard ",
+struct chip_operations mainboard_Iwill_DK8S2_ops = {
+ CHIP_NAME("Iwill DK8S2 mainboard")
};
diff --git a/src/mainboard/Iwill/DK8S2/mptable.c b/src/mainboard/Iwill/DK8S2/mptable.c
index bd9df2e3ac..34e6037c21 100644
--- a/src/mainboard/Iwill/DK8S2/mptable.c
+++ b/src/mainboard/Iwill/DK8S2/mptable.c
@@ -4,11 +4,11 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "LNXI ";
- static const char productid[12] = "HDAMA ";
+ static const char oem[8] = "IWILL ";
+ static const char productid[12] = "DK8X ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
@@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
-
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/Iwill/DK8X/Config.lb b/src/mainboard/Iwill/DK8X/Config.lb
index f95725ecbb..903f5c6c62 100644
--- a/src/mainboard/Iwill/DK8X/Config.lb
+++ b/src/mainboard/Iwill/DK8X/Config.lb
@@ -1,110 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-#default MAINBOARD_PART_NUMBER="HDAMA"
-#default MAINBOARD_VENDOR="ARIMA"
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -123,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -145,15 +37,12 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
-#cpu k8 end
##
## Build the objects we have code for in this directory.
##
-#object mainboard.o
driver mainboard.o
-#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
@@ -161,41 +50,41 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -207,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-mainboardinit cpu/k8/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -229,9 +113,12 @@ end
##
## Setup RAM
##
-mainboardinit cpu/k8/enable_mmx_sse.inc
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -306,9 +193,3 @@ chip northbridge/amd/amdk8
end
end
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-
diff --git a/src/mainboard/Iwill/DK8X/auto.c b/src/mainboard/Iwill/DK8X/auto.c
index 9889f23229..b8ca3c82ba 100644
--- a/src/mainboard/Iwill/DK8X/auto.c
+++ b/src/mainboard/Iwill/DK8X/auto.c
@@ -1,25 +1,51 @@
#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
-#include <cpu/p6/apic.h>
#include <arch/io.h>
-#include <device/pnp.h>
+#include <device/pnp_def.h>
#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
+#include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
-#define SIO_BASE 0x2e
+#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -103,68 +129,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-static void enable_lapic(void)
-{
-
- msr_t msr;
- msr = rdmsr(0x1b);
- msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
- wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
- unsigned apicid;
- apicid = apic_read(APIC_ID) >> 24;
-
- /* Send an APIC INIT to myself */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* Deassert the APIC INIT */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* If I haven't halted spin forever */
- for(;;) {
- hlt();
- }
-}
-
-#define PC87360_FDC 0x00
-#define PC87360_PP 0x01
-#define PC87360_SP2 0x02
-#define PC87360_SP1 0x03
-#define PC87360_SWC 0x04
-#define PC87360_KBCM 0x05
-#define PC87360_KBCK 0x06
-#define PC87360_GPIO 0x07
-#define PC87360_ACB 0x08
-#define PC87360_FSCM 0x09
-#define PC87360_WDT 0x0A
-
-static void pc87360_enable_serial(void)
-{
- pnp_set_logical_device(SIO_BASE, PC87360_SP1);
- pnp_set_enable(SIO_BASE, 1);
- pnp_set_iobase0(SIO_BASE, 0x3f8);
-}
-
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@@ -189,22 +158,38 @@ static void main(void)
},
#endif
};
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- enable_lapic();
- init_timer();
- if (!boot_cpu()) {
- stop_this_cpu();
+
+ int needs_reset;
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
- pc87360_enable_serial();
+ /* Setup the console */
+ pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_default_resource_map();
- setup_coherent_ht_domain();
- enumerate_ht_chain(0);
- distinguish_cpu_resets(0);
-
+ needs_reset = setup_coherent_ht_domain();
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
+
#if 0
print_pci_devices();
#endif
@@ -212,6 +197,7 @@ static void main(void)
#if 0
dump_spd_registers(&cpu[0]);
#endif
+
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
diff --git a/src/mainboard/Iwill/DK8X/chip.h b/src/mainboard/Iwill/DK8X/chip.h
index c0f74846ef..7710024cca 100644
--- a/src/mainboard/Iwill/DK8X/chip.h
+++ b/src/mainboard/Iwill/DK8X/chip.h
@@ -1,5 +1,5 @@
-extern struct chip_operations mainboard_arima_hdama_control;
+extern struct chip_operations mainboard_Iwill_DK8X_ops;
-struct mainboard_arima_hdama_config {
+struct mainboard_Iwill_DK8X_config {
int nothing;
};
diff --git a/src/mainboard/Iwill/DK8X/cmos.layout b/src/mainboard/Iwill/DK8X/cmos.layout
index 5ba4c032c1..1ab6187288 100644
--- a/src/mainboard/Iwill/DK8X/cmos.layout
+++ b/src/mainboard/Iwill/DK8X/cmos.layout
@@ -29,6 +29,9 @@ entries
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
@@ -36,7 +39,15 @@ entries
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
-1008 16 h 0 check_sum
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
enumerations
@@ -66,9 +77,19 @@ enumerations
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
+8 0 200Mhz
+8 1 166Mhz
+8 2 133Mhz
+8 3 100Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
checksums
-checksum 392 1007 1008
-
-
+checksum 392 983 984
diff --git a/src/mainboard/Iwill/DK8X/mainboard.c b/src/mainboard/Iwill/DK8X/mainboard.c
index 845285c881..a1b05d0943 100644
--- a/src/mainboard/Iwill/DK8X/mainboard.c
+++ b/src/mainboard/Iwill/DK8X/mainboard.c
@@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-struct chip_operations mainboard_arima_hdama_control = {
- .name = "Arima HDAMA mainboard ",
+struct chip_operations mainboard_Iwill_DK8X_ops = {
+ CHIP_NAME("Iwill DK8X mainboard")
};
diff --git a/src/mainboard/Iwill/DK8X/mptable.c b/src/mainboard/Iwill/DK8X/mptable.c
index bd9df2e3ac..34e6037c21 100644
--- a/src/mainboard/Iwill/DK8X/mptable.c
+++ b/src/mainboard/Iwill/DK8X/mptable.c
@@ -4,11 +4,11 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
- static const char oem[8] = "LNXI ";
- static const char productid[12] = "HDAMA ";
+ static const char oem[8] = "IWILL ";
+ static const char productid[12] = "DK8X ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
@@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
-
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb
index c9a1d4203e..9b003978b5 100644
--- a/src/mainboard/amd/quartet/Config.lb
+++ b/src/mainboard/amd/quartet/Config.lb
@@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c
index 67bc959496..6a3b2194e7 100644
--- a/src/mainboard/amd/quartet/auto.c
+++ b/src/mainboard/amd/quartet/auto.c
@@ -7,7 +7,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -16,13 +17,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@@ -41,7 +44,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
-
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -144,13 +150,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "fakespd.c"
#endif
-#include "northbridge/amd/amdk8/setup_resource_map.c"
+// #include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
-
#include "northbridge/amd/amdk8/coherent_ht.c"
-
#include "sdram/generic_sdram.c"
-
#include "resourcemap.c" /* quartet does not want the default */
#define RC0 ((1<<1)<<8)
@@ -163,7 +166,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM2 0x52
#define DIMM3 0x53
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
{
@@ -215,22 +218,30 @@ static void main(void)
int needs_reset;
- enable_lapic();
- init_timer();
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
-
- distinguish_cpu_resets();
+ distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
-
+ /* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_quartet_resource_map();
needs_reset = setup_coherent_ht_domain();
// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
diff --git a/src/mainboard/amd/quartet/chip.h b/src/mainboard/amd/quartet/chip.h
index 526dcc4515..59c2edff48 100644
--- a/src/mainboard/amd/quartet/chip.h
+++ b/src/mainboard/amd/quartet/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_amd_quartet_control;
+extern struct chip_operations mainboard_amd_quartet_ops;
struct mainboard_amd_quartet_config {
int nothing;
diff --git a/src/mainboard/amd/quartet/mainboard.c b/src/mainboard/amd/quartet/mainboard.c
index 4071c3b93d..e72ff2c43a 100644
--- a/src/mainboard/amd/quartet/mainboard.c
+++ b/src/mainboard/amd/quartet/mainboard.c
@@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-struct chip_operations mainboard_amd_quartet_control = {
- .name = "AMD Quartet mainboard ",
+struct chip_operations mainboard_amd_quartet_ops = {
+ CHIP_NAME("AMD Quartet mainboard ")
};
diff --git a/src/mainboard/amd/quartet/mptable.c b/src/mainboard/amd/quartet/mptable.c
index 03ff598877..9d3ea13127 100644
--- a/src/mainboard/amd/quartet/mptable.c
+++ b/src/mainboard/amd/quartet/mptable.c
@@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
@@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -82,24 +82,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
-
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -216,17 +217,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/amd/serenade/Config.lb b/src/mainboard/amd/serenade/Config.lb
index 79427896c5..4fbf6310b0 100644
--- a/src/mainboard/amd/serenade/Config.lb
+++ b/src/mainboard/amd/serenade/Config.lb
@@ -46,22 +46,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@@ -76,11 +76,11 @@ ldscript /cpu/x86/32bit/entry32.lds
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
diff --git a/src/mainboard/amd/serenade/auto.c b/src/mainboard/amd/serenade/auto.c
index 85ee737fd1..fb595f7acd 100644
--- a/src/mainboard/amd/serenade/auto.c
+++ b/src/mainboard/amd/serenade/auto.c
@@ -6,7 +6,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -15,13 +16,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -41,6 +44,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+/*
+ * GPIO16 of 8111 will control H0_MEMRESET_L
+ * GPIO17 of 8111 will control H1_MEMRESET_L
+ */
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -126,12 +133,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@@ -156,24 +159,31 @@ static void main(void)
},
#endif
};
- int needs_reset;
-
- enable_lapic();
- init_timer();
-
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
+ int needs_reset;
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
-
+ /* Setup the console */
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
#if 0
print_pci_devices();
#endif
diff --git a/src/mainboard/amd/serenade/chip.h b/src/mainboard/amd/serenade/chip.h
index 066852b37a..9f244772d0 100644
--- a/src/mainboard/amd/serenade/chip.h
+++ b/src/mainboard/amd/serenade/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_amd_serenade_control;
+extern struct chip_operations mainboard_amd_serenade_ops;
struct mainboard_amd_serenade_config {
int nothing;
diff --git a/src/mainboard/amd/serenade/mainboard.c b/src/mainboard/amd/serenade/mainboard.c
index 750438ce28..ab3a800b52 100644
--- a/src/mainboard/amd/serenade/mainboard.c
+++ b/src/mainboard/amd/serenade/mainboard.c
@@ -3,11 +3,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-struct chip_operations mainboard_amd_serenade_control = {
- .name = "AMD Serenade mainboard ",
+struct chip_operations mainboard_amd_serenade_ops = {
+ CHIP_NAME("AMD Serenade mainboard ")
};
diff --git a/src/mainboard/amd/serenade/mptable.c b/src/mainboard/amd/serenade/mptable.c
index 6e3b6e2557..b00eb2b082 100644
--- a/src/mainboard/amd/serenade/mptable.c
+++ b/src/mainboard/amd/serenade/mptable.c
@@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "AMD ";
@@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb
index ad8bad9325..7f845725e3 100644
--- a/src/mainboard/amd/solo/Config.lb
+++ b/src/mainboard/amd/solo/Config.lb
@@ -47,22 +47,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h "
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
diff --git a/src/mainboard/amd/solo/mainboard.c b/src/mainboard/amd/solo/mainboard.c
index 41ee605695..058a1aff01 100644
--- a/src/mainboard/amd/solo/mainboard.c
+++ b/src/mainboard/amd/solo/mainboard.c
@@ -4,30 +4,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
- .scan_bus = root_dev_scan_bus,
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev->ops = &mainboard_operations;
-}
-
struct chip_operations mainboard_amd_solo_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("AMD Solo7 mainboard")
};
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index 0799be0117..f812868f4a 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -32,7 +32,11 @@ default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-arch i386 end
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
##
## Build the objects we have code for in this directory.
@@ -77,11 +81,11 @@ ldscript /cpu/x86/32bit/entry32.lds
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
diff --git a/src/mainboard/arima/hdama/cmos.layout b/src/mainboard/arima/hdama/cmos.layout
index ea027282c4..1ab6187288 100644
--- a/src/mainboard/arima/hdama/cmos.layout
+++ b/src/mainboard/arima/hdama/cmos.layout
@@ -93,5 +93,3 @@ enumerations
checksums
checksum 392 983 984
-
-
diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c
index 95ed7368f9..69b738e2b4 100644
--- a/src/mainboard/arima/hdama/mainboard.c
+++ b/src/mainboard/arima/hdama/mainboard.c
@@ -7,315 +7,10 @@
#include <part/hard_reset.h>
#include <device/smbus.h>
#include <delay.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
#include "chip.h"
-#include "pc80/mc146818rtc.h"
-
-
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-#if 0
-static void handle_smbus_error(int value, const char *msg)
-{
- if (value >= 0) {
- return;
- }
- switch(value) {
- case SMBUS_WAIT_UNTIL_READY_TIMEOUT:
- printk_emerg("SMBUS wait until ready timed out - resetting...");
- hard_reset();
- break;
- case SMBUS_WAIT_UNTIL_DONE_TIMEOUT:
- printk_emerg("SMBUS wait until done timed out - resetting...");
- hard_reset();
- break;
- default:
- die(msg);
- break;
- }
-}
-
-#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */
-#define ADM1026_REG_CONFIG1 0x00
-#define CFG1_MONITOR 0x01
-#define CFG1_INT_ENABLE 0x02
-#define CFG1_INT_CLEAR 0x04
-#define CFG1_AIN8_9 0x08
-#define CFG1_THERM_HOT 0x10
-#define CFT1_DAC_AFC 0x20
-#define CFG1_PWM_AFC 0x40
-#define CFG1_RESET 0x80
-#define ADM1026_REG_CONFIG2 0x01
-#define ADM1026_REG_CONFIG3 0x07
-
-
-
-#define BILLION 1000000000UL
-
-static void verify_cpu_voltage(const char *name,
- device_t dev, unsigned int reg,
- unsigned factor, unsigned cpu_volts, unsigned delta)
-{
- unsigned nvolts_lo, nvolts_hi;
- unsigned cpuvolts_hi, cpuvolts_lo;
- int value;
- int loops;
-
- loops = 1000;
- do {
- value = smbus_read_byte(dev, reg);
- handle_smbus_error(value, "SMBUS read byte failed");
- } while ((--loops > 0) && value == 0);
- /* Convert the byte value to nanoVolts.
- * My accuracy is nowhere near that good but I don't
- * have to round so the math is simple.
- * I can only go up to about 4.2 Volts this way so my range is
- * limited.
- */
- nvolts_lo = ((unsigned)value * factor);
- nvolts_hi = nvolts_lo + factor - 1;
- /* Get the range of acceptable cpu voltage values */
- cpuvolts_lo = cpu_volts - delta;
- cpuvolts_hi = cpu_volts + delta;
- if ((nvolts_lo < cpuvolts_lo) || (nvolts_hi > cpuvolts_hi)) {
- printk_emerg("%s at (%u.%09u-%u.%09u)Volts expected %u.%09u+/-%u.%09uVolts\n",
- name,
- nvolts_lo/BILLION, nvolts_lo%BILLION,
- nvolts_hi/BILLION, nvolts_hi%BILLION,
- cpu_volts/BILLION, cpu_volts%BILLION,
- delta/BILLION, delta%BILLION);
- die("");
- }
- printk_info("%s at (%u.%09u-%u.%09u)Volts\n",
- name,
- nvolts_lo/BILLION, nvolts_lo%BILLION,
- nvolts_hi/BILLION, nvolts_hi%BILLION);
-
-}
-
-static void adm1026_enable_monitoring(device_t dev)
-{
- int result;
- result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
- handle_smbus_error(result, "ADM1026: cannot read config1");
-
- result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
- result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
- handle_smbus_error(result, "ADM1026: cannot write to config1");
-
- result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
- handle_smbus_error(result, "ADM1026: cannot reread config1");
- if (!(result & CFG1_MONITOR)) {
- die("ADM1026: monitoring would not enable");
- }
-}
-
-
-static unsigned k8_cpu_volts(void)
-{
- unsigned volts = ~0;
- if (is_cpu_c0()) {
- volts = 1500000000;
- }
- if (is_cpu_b3()) {
- volts = 1550000000;
- }
- return volts;
-}
-
-static void verify_cpu_voltages(device_t dev)
-{
- unsigned cpu_volts;
- unsigned delta;
-#if 0
- delta = 50000000;
-#else
- delta = 75000000;
-#endif
- cpu_volts = k8_cpu_volts();
- if (cpu_volts == ~0) {
- printk_info("Required cpu voltage unknwon not checking\n");
- return;
- }
- /* I need to read registers 0x37 == Ain7CPU1 core 0x2d == VcppCPU0 core */
- /* CPU1 core
- * The sensor has a range of 0-2.5V and reports in
- * 256 distinct steps.
- */
- verify_cpu_voltage("CPU1 Vcore", dev, 0x37, 9765625,
- cpu_volts, delta);
- /* CPU0 core
- * The sensor has range of 0-3.0V and reports in
- * 256 distinct steps.
- */
- verify_cpu_voltage("CPU0 Vcore", dev, 0x2d, 11718750,
- cpu_volts, delta);
-}
-
-#define SMBUS_MUX 0x70
-
-static void do_verify_cpu_voltages(void)
-{
- device_t smbus_dev;
- device_t mux, sensor;
- struct device_path mux_path, sensor_path;
- int result;
- int mux_setting;
-
- /* Find the smbus controller */
- smbus_dev = dev_find_device(0x1022, 0x746b, 0);
- if (!smbus_dev) {
- die("SMBUS controller not found\n");
- }
-
- /* Find the smbus mux */
- mux_path.type = DEVICE_PATH_I2C;
- mux_path.u.i2c.device = SMBUS_MUX;
- mux = find_dev_path(smbus_dev, &mux_path);
- if (!mux) {
- die("SMBUS mux not found\n");
- }
-
- /* Find the adm1026 sensor */
- sensor_path.type = DEVICE_PATH_I2C;
- sensor_path.u.i2c.device = ADM1026_DEVICE;
- sensor = find_dev_path(mux, &sensor_path);
- if (!sensor) {
- die("ADM1026 not found\n");
- }
-
- /* Set the mux to see the temperature sensors */
- mux_setting = 1;
- result = smbus_send_byte(mux, mux_setting);
- handle_smbus_error(result, "SMBUS send byte failed\n");
-
- result = smbus_recv_byte(mux);
- handle_smbus_error(result, "SMBUS recv byte failed\n");
- if (result != mux_setting) {
- printk_emerg("SMBUS mux would not set to %d\n", mux_setting);
- die("");
- }
-
- adm1026_enable_monitoring(sensor);
-
- /* It takes 11.38ms to read a new voltage sensor value */
- mdelay(12);
-
- /* Read the cpu voltages and make certain everything looks sane */
- verify_cpu_voltages(sensor);
-}
-#else
-#define do_verify_cpu_voltages() do {} while(0)
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
- do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-static void enable_dev(struct device *dev)
-{
- dev->ops = &mainboard_operations;
-}
struct chip_operations mainboard_arima_hdama_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Arima Hdama mainboard")
};
diff --git a/src/mainboard/densitron/dpx114/Config.lb b/src/mainboard/densitron/dpx114/Config.lb
index 0450b2b1b9..05698b117d 100644
--- a/src/mainboard/densitron/dpx114/Config.lb
+++ b/src/mainboard/densitron/dpx114/Config.lb
@@ -1,86 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
-object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -99,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -126,49 +42,49 @@ arch i386 end
## Build the objects we have code for in this directory.
##
-
driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -O -mcpu=c3 ./auto.E "
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-# mainboardinit cpu/p6/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -202,7 +113,10 @@ end
##
## Setup RAM
##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -210,32 +124,24 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
-northbridge via/vt8601 "vt8601"
-# pci 0:0.0
-# pci 0:1.0
- southbridge via/vt8231 "vt8231"
-# pci 0:11.0
-# pci 0:11.1
-# pci 0:11.2
-# pci 0:11.3
-# pci 0:11.4
-# pci 0:11.5
-# pci 0:11.6
-# pci 0:12.0
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- register "enable_com_ports" = "1"
- register "enable_keyboard" = "0"
- register "enable_nvram" = "1"
+chip northbridge/via/vt8601
+ device pci_domain 0 on
+ chip southbridge/via/vt8231
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ register "enable_com_ports" = "1"
+ register "enable_keyboard" = "0"
+ register "enable_nvram" = "1"
+# device pci 0:11.0 on end
+# device pci 0:11.1 on end
+# device pci 0:11.2 on end
+# device pci 0:11.3 on end
+# device pci 0:11.4 on end
+# device pci 0:11.5 on end
+# device pci 0:11.6 on end
+# device pci 0:12.0 on end
+ end
+ end
+ chip cpu/via/model_centaur
end
end
-
-cpu p6 "cpu0"
-
-end
-
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
diff --git a/src/mainboard/densitron/dpx114/auto.c b/src/mainboard/densitron/dpx114/auto.c
index 7b1c637cd0..a1b3818b93 100644
--- a/src/mainboard/densitron/dpx114/auto.c
+++ b/src/mainboard/densitron/dpx114/auto.c
@@ -2,7 +2,9 @@
#include <stdint.h>
#include <device/pci_def.h>
-#include <cpu/p6/apic.h>
+#if 0
+#include <cpu/x86/lapic.h>
+#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@@ -11,7 +13,8 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
-#include "cpu/p6/earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
/*
*/
@@ -23,10 +26,22 @@ void udelay(int usecs)
}
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "debug.c"
+#include "southbridge/via/vt8231/vt8231_early_smbus.c"
+
+
#include "southbridge/via/vt8231/vt8231_early_serial.c"
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ unsigned char c;
+ c = smbus_read_byte(device, address);
+ return c;
+}
+
+#include "northbridge/via/vt8601/raminit.c"
+
static void enable_mainboard_devices(void)
{
@@ -68,16 +83,22 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
-static void main(void)
+static void main(unsigned long bist)
{
unsigned long x;
- /* init_timer();*/
- outb(5, 0x80);
-
- enable_vt8231_serial();
+ if (bist == 0) {
+ early_mtrr_init();
+ }
+ enable_vt8231_serial();
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* init_timer();*/
+ outb(5, 0x80);
enable_mainboard_devices();
enable_smbus();
@@ -102,5 +123,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
- early_mtrr_init();
}
diff --git a/src/mainboard/densitron/dpx114/chip.h b/src/mainboard/densitron/dpx114/chip.h
index 8f7eae8bee..10beb176b0 100644
--- a/src/mainboard/densitron/dpx114/chip.h
+++ b/src/mainboard/densitron/dpx114/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_densitron_dpx114_control;
+extern struct chip_operations mainboard_densitron_dpx114_ops;
struct mainboard_densitron_dpx114_config {
int nothing;
diff --git a/src/mainboard/densitron/dpx114/failover.c b/src/mainboard/densitron/dpx114/failover.c
index bd0df4e89d..bdcb9eaed2 100644
--- a/src/mainboard/densitron/dpx114/failover.c
+++ b/src/mainboard/densitron/dpx114/failover.c
@@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
-#include "cpu/p6/boot_cpu.c"
-static void main(void)
+static unsigned long main(unsigned long bist)
{
- /* for now, just always assume failure */
-
-#if 0
- /* Is this a cpu reset? */
- if (cpu_init_detected()) {
- if (last_boot_normal()) {
- asm("jmp __normal_image");
- } else {
- asm("jmp __cpu_reset");
- }
- }
-
/* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- asm("jmp __normal_image");
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
}
-#endif
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
}
diff --git a/src/mainboard/densitron/dpx114/mainboard.c b/src/mainboard/densitron/dpx114/mainboard.c
index 188da9216e..f973012ca0 100644
--- a/src/mainboard/densitron/dpx114/mainboard.c
+++ b/src/mainboard/densitron/dpx114/mainboard.c
@@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
#include "chip.h"
-static int
-mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
- .enable = 0,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainboard_operations;
-}
-struct chip_operations mainboard_via_epia_control = {
- .enable_dev = enable_dev,
- .name = "VIA EPIA mainboard ",
+struct chip_operations mainboard_densitron_dpx114_ops = {
+ CHIP_NAME("Densitron DPX114 mainboard ")
};
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
index 9871632bfb..2564eeff2b 100644
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ b/src/mainboard/digitallogic/adl855pc/Config.lb
@@ -1,86 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
-object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -99,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -126,49 +42,49 @@ arch i386 end
## Build the objects we have code for in this directory.
##
-
driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -mcpu=p4 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -O -mcpu=p4 ./auto.E "
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -180,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-# mainboardinit cpu/p6/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -203,7 +114,7 @@ end
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/emable_mmx.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
@@ -273,8 +184,8 @@ chip northbridge/intel/i855pm
end
end
device apic_cluster 0 on
- device cpu/intel/socket_mPGA479M
- apic 0
+ chip cpu/intel/socket_mPGA479M
+ device apic 0 on end
end
end
end
diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/auto.c
index f2e183615b..1af77f4504 100644
--- a/src/mainboard/digitallogic/adl855pc/auto.c
+++ b/src/mainboard/digitallogic/adl855pc/auto.c
@@ -5,7 +5,10 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
+#if 0
#include <arch/smp/lapic.h>
+#endif
+#include <arch/hlt.h>
//#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -14,16 +17,16 @@
#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
#include "northbridge/intel/i855pm/raminit.h"
-#if 1
+#if 0
#include "cpu/p6/apic_timer.c"
#include "lib/delay.c"
#endif
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/i855pm/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/p6/earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -57,7 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i855pm/reset_test.c"
#include "sdram/generic_sdram.c"
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{
@@ -66,15 +69,21 @@ static void main(void)
},
};
-#if 1
- enable_lapic();
- init_timer();
+ if (bist == 0) {
+ early_mtrr_init();
+#if 0
+ enable_lapic();
+ init_timer();
#endif
+ }
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
#if 0
print_pci_devices();
#endif
diff --git a/src/mainboard/digitallogic/adl855pc/chip.h b/src/mainboard/digitallogic/adl855pc/chip.h
index e660951a9b..0ed8089561 100644
--- a/src/mainboard/digitallogic/adl855pc/chip.h
+++ b/src/mainboard/digitallogic/adl855pc/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_digitallogic_adl855pc_control;
+extern struct chip_operations mainboard_digitallogic_adl855pc_ops;
struct mainboard_digitallogic_adl855pc_config {
int nothing;
diff --git a/src/mainboard/digitallogic/adl855pc/failover.c b/src/mainboard/digitallogic/adl855pc/failover.c
index bd0df4e89d..bdcb9eaed2 100644
--- a/src/mainboard/digitallogic/adl855pc/failover.c
+++ b/src/mainboard/digitallogic/adl855pc/failover.c
@@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
-#include "cpu/p6/boot_cpu.c"
-static void main(void)
+static unsigned long main(unsigned long bist)
{
- /* for now, just always assume failure */
-
-#if 0
- /* Is this a cpu reset? */
- if (cpu_init_detected()) {
- if (last_boot_normal()) {
- asm("jmp __normal_image");
- } else {
- asm("jmp __cpu_reset");
- }
- }
-
/* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- asm("jmp __normal_image");
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
}
-#endif
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
}
diff --git a/src/mainboard/digitallogic/adl855pc/mainboard.c b/src/mainboard/digitallogic/adl855pc/mainboard.c
index 1ef4af1d38..a818240be1 100644
--- a/src/mainboard/digitallogic/adl855pc/mainboard.c
+++ b/src/mainboard/digitallogic/adl855pc/mainboard.c
@@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
#include "chip.h"
-static int
-mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
- .enable = 0,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainboard_operations;
-}
-struct chip_operations mainboard_digitallogic_adl855pc_control = {
- .enable_dev = enable_dev,
- .name = "Digital Logic ADL855PC mainboard ",
+struct chip_operations mainboard_digitallogic_adl855pc_ops = {
+ CHIP_NAME("Digital Logic ADL855PC mainboard ")
};
diff --git a/src/mainboard/emulation/qemu-i386/auto.c b/src/mainboard/emulation/qemu-i386/auto.c
index a4259df0fe..d2fa623d68 100644
--- a/src/mainboard/emulation/qemu-i386/auto.c
+++ b/src/mainboard/emulation/qemu-i386/auto.c
@@ -7,6 +7,8 @@
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
diff --git a/src/mainboard/emulation/qemu-i386/mainboard.c b/src/mainboard/emulation/qemu-i386/mainboard.c
index 173f8aa2ab..83ea657a78 100644
--- a/src/mainboard/emulation/qemu-i386/mainboard.c
+++ b/src/mainboard/emulation/qemu-i386/mainboard.c
@@ -3,34 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
#include "chip.h"
-static int mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev->ops = &mainboard_operations;
-}
-
struct chip_operations mainboard_emulation_qemu_i386_ops = {
- .enable_dev = enable_dev,
- //.name = "qemu mainboard ",
+ CHIP_NAME("qemu mainboard ")
};
diff --git a/src/mainboard/ibm/e325/Config.lb b/src/mainboard/ibm/e325/Config.lb
index 49ec1ccbe0..c1514000fd 100644
--- a/src/mainboard/ibm/e325/Config.lb
+++ b/src/mainboard/ibm/e325/Config.lb
@@ -1,123 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -136,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -158,7 +37,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
-#cpu k8 end
##
## Build the objects we have code for in this directory.
@@ -172,42 +50,41 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h "
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -219,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-mainboardinit cpu/k8/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -241,9 +113,12 @@ end
##
## Setup RAM
##
-mainboardinit cpu/k8/enable_mmx_sse.inc
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -332,10 +207,3 @@ chip northbridge/amd/amdk8
end
end
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-
diff --git a/src/mainboard/ibm/e325/Options.lb b/src/mainboard/ibm/e325/Options.lb
index 807260cc55..7a00b5b150 100644
--- a/src/mainboard/ibm/e325/Options.lb
+++ b/src/mainboard/ibm/e325/Options.lb
@@ -117,6 +117,8 @@ default CONFIG_IOAPIC=1
##
default MAINBOARD_PART_NUMBER="E325"
default MAINBOARD_VENDOR="IBM"
+#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
###
### LinuxBIOS layout values
@@ -133,7 +135,7 @@ default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
-default HEAP_SIZE=0x4000
+default HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
diff --git a/src/mainboard/ibm/e325/auto.c b/src/mainboard/ibm/e325/auto.c
index 2c80a7d0ad..dbbcbf597b 100644
--- a/src/mainboard/ibm/e325/auto.c
+++ b/src/mainboard/ibm/e325/auto.c
@@ -6,7 +6,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -15,13 +16,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87366/pc87366_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
@@ -127,12 +130,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
@@ -157,24 +156,30 @@ static void main(void)
},
#endif
};
- int needs_reset;
-
- enable_lapic();
- init_timer();
-
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
+ int needs_reset;
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
-
+ /* Setup the console */
pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
#if 0
print_pci_devices();
#endif
@@ -224,5 +229,4 @@ static void main(void)
/* Check the first 1M */
ram_check(0x00000000, 0x001000000);
#endif
-
}
diff --git a/src/mainboard/ibm/e325/chip.h b/src/mainboard/ibm/e325/chip.h
index c34253735f..589d0284aa 100644
--- a/src/mainboard/ibm/e325/chip.h
+++ b/src/mainboard/ibm/e325/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_ibm_e325_control;
+extern struct chip_operations mainboard_ibm_e325_ops;
struct mainboard_ibm_e325_config {
int nothing;
diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c
index 31f5bdcb18..2ace7c3e21 100644
--- a/src/mainboard/ibm/e325/mainboard.c
+++ b/src/mainboard/ibm/e325/mainboard.c
@@ -3,11 +3,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-struct chip_operations mainboard_ibm_e325_control = {
- .name = "IBM E325 mainboard ",
+struct chip_operations mainboard_ibm_e325_ops = {
+ CHIP_NAME("IBM E325 mainboard ")
};
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index bc9d52f262..6ad8b945b4 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "IBM ";
@@ -35,7 +35,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -83,20 +83,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -164,10 +166,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/newisys/khepri/Config.lb b/src/mainboard/newisys/khepri/Config.lb
index 81b943c285..77e1ec8d05 100644
--- a/src/mainboard/newisys/khepri/Config.lb
+++ b/src/mainboard/newisys/khepri/Config.lb
@@ -1,123 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="Khepri 2100"
-default MAINBOARD_VENDOR="Newisys"
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -136,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -158,7 +37,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
arch i386 end
-#cpu k8 end
##
## Build the objects we have code for in this directory.
@@ -174,42 +52,41 @@ dir /drivers/trident/blade3d
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -221,11 +98,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-mainboardinit cpu/k8/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -243,9 +115,12 @@ end
##
## Setup RAM
##
-mainboardinit cpu/k8/enable_mmx_sse.inc
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -334,10 +209,3 @@ chip northbridge/amd/amdk8
end
end
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-
diff --git a/src/mainboard/newisys/khepri/auto.c b/src/mainboard/newisys/khepri/auto.c
index 6e6dec743f..1aa151f906 100644
--- a/src/mainboard/newisys/khepri/auto.c
+++ b/src/mainboard/newisys/khepri/auto.c
@@ -1,4 +1,6 @@
#define ASSEMBLY 1
+#undef MAXIMUM_CONSOLE_LOGLEVEL
+#undef DEFAULT_CONSOLE_LOGLEVEL
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
@@ -7,7 +9,8 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
@@ -16,13 +19,15 @@
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
@@ -126,14 +131,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "sdram/generic_sdram.c"
-#include "resourcemap.c" /* newisys khepri does not want the default */
+/* newisys khepri does not want the default */
+#include "resourcemap.c"
-static void main(void)
+static void main(unsigned long bist)
{
- /*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
static const struct mem_controller cpu[] = {
{
.node_id = 0,
@@ -154,19 +156,30 @@ static void main(void)
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
};
+
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+ /* Has this cpu already booted? */
+ if (cpu_init_detected()) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
+ /* Setup the console */
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_khepri_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
diff --git a/src/mainboard/newisys/khepri/chip.h b/src/mainboard/newisys/khepri/chip.h
index cb4a806d66..f4889d6a65 100644
--- a/src/mainboard/newisys/khepri/chip.h
+++ b/src/mainboard/newisys/khepri/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_newisys_khepri_control;
+extern struct chip_operations mainboard_newisys_khepri_ops;
struct mainboard_newisys_khepri_config {
int nothing;
diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c
index 67ebd9add2..16350b2acf 100644
--- a/src/mainboard/newisys/khepri/mainboard.c
+++ b/src/mainboard/newisys/khepri/mainboard.c
@@ -3,12 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
-#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-struct chip_operations mainboard_newisys_khepri_control = {
- .name = "Newisys Khepri mainboard ",
+struct chip_operations mainboard_newisys_khepri_ops = {
+ CHIP_NAME("Newisys Khepri mainboard ")
};
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 314a04160b..8d7d519654 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -4,7 +4,7 @@
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "NEWISYS ";
@@ -33,7 +33,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
@@ -86,20 +86,22 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
device_t dev;
- uint32_t base;
+ struct resource *res;
/* 8131 apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x03, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
/* 8131 apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 0x04, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
@@ -216,17 +218,16 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
diff --git a/src/mainboard/technologic/ts5300/Config.lb b/src/mainboard/technologic/ts5300/Config.lb
index d0ff85f1df..aeb7dc1d59 100644
--- a/src/mainboard/technologic/ts5300/Config.lb
+++ b/src/mainboard/technologic/ts5300/Config.lb
@@ -134,22 +134,22 @@ driver mainboard.o
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -O -mcpu=c3 ./auto.E "
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@@ -218,5 +218,6 @@ chip northbridge/amd/sc520
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
end
- chip cpu/amd/sc520
+ chip cpu/amd/sc520
+ end
end
diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c
index 38b6a4ca82..e28f9715b8 100644
--- a/src/mainboard/technologic/ts5300/mainboard.c
+++ b/src/mainboard/technologic/ts5300/mainboard.c
@@ -3,35 +3,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
-#include <arch/io.h>
#include "chip.h"
-static int
-mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainbaord_operations;
-}
-
struct chip_operations mainboard_technologic_ts5300_control = {
- .enable_dev = enable_dev,
- .name = "Technologic Systems TS5300 mainboard ",
+ CHIP_NAME("Technologic Systems TS5300 mainboard ")
};
diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c
index 7898d2e7e4..29cf899be8 100644
--- a/src/mainboard/tyan/s2735/mainboard.c
+++ b/src/mainboard/tyan/s2735/mainboard.c
@@ -119,30 +119,6 @@ static void vga_fixup(void) {
}
*/
-static int
-mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainboard_operations;
-}
-
struct chip_operations mainboard_tyan_s2735_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s2735 mainboard")
};
-
diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c
index ce2405e3cd..1270b59146 100644
--- a/src/mainboard/tyan/s2850/mainboard.c
+++ b/src/mainboard/tyan/s2850/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s2850_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s2850 mainboard")
};
diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c
index a0014f3fae..dd27224fbe 100644
--- a/src/mainboard/tyan/s2880/mainboard.c
+++ b/src/mainboard/tyan/s2880/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s2880_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tayn s2880 mainboard")
};
diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c
index e058fe6a6d..b88a992e84 100644
--- a/src/mainboard/tyan/s2881/mainboard.c
+++ b/src/mainboard/tyan/s2881/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s2881_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s2881 mainboard")
};
diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c
index b076acdd1a..73aeda4107 100644
--- a/src/mainboard/tyan/s2882/auto.c
+++ b/src/mainboard/tyan/s2882/auto.c
@@ -126,11 +126,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-//#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
#define FIRST_CPU 1
@@ -196,7 +195,7 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
-// report_bist_failure(bist);
+ report_bist_failure(bist);
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c
index 8bc1ac9b9a..9bee33d598 100644
--- a/src/mainboard/tyan/s2882/mainboard.c
+++ b/src/mainboard/tyan/s2882/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s2882_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s2882 mainboard")
};
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index a51278b06a..080a9dc03d 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s2885_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s2885 mainboard")
};
diff --git a/src/mainboard/tyan/s4880/auto.c b/src/mainboard/tyan/s4880/auto.c
index a19b4fa4bc..b083ce0c91 100644
--- a/src/mainboard/tyan/s4880/auto.c
+++ b/src/mainboard/tyan/s4880/auto.c
@@ -256,7 +256,7 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
-// report_bist_failure(bist);
+ report_bist_failure(bist);
setup_s4880_resource_map();
needs_reset = setup_coherent_ht_domain();
diff --git a/src/mainboard/tyan/s4880/mainboard.c b/src/mainboard/tyan/s4880/mainboard.c
index 1c3e40c13a..cec60e7af3 100644
--- a/src/mainboard/tyan/s4880/mainboard.c
+++ b/src/mainboard/tyan/s4880/mainboard.c
@@ -163,111 +163,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s4880_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s4880 mainboard")
};
diff --git a/src/mainboard/tyan/s4882/mainboard.c b/src/mainboard/tyan/s4882/mainboard.c
index 59723ac4e3..39696b8741 100644
--- a/src/mainboard/tyan/s4882/mainboard.c
+++ b/src/mainboard/tyan/s4882/mainboard.c
@@ -162,112 +162,6 @@ enable(struct chip *chip, enum chip_pass pass)
}
#endif
-
-#undef DEBUG
-#define DEBUG 0
-#if DEBUG
-static void debug_init(device_t dev)
-{
- unsigned bus;
- unsigned devfn;
-#if 0
- for(bus = 0; bus < 256; bus++) {
- for(devfn = 0; devfn < 256; devfn++) {
- int i;
- dev = dev_find_slot(bus, devfn);
- if (!dev) {
- continue;
- }
- if (!dev->enabled) {
- continue;
- }
- printk_info("%02x:%02x.%0x aka %s\n",
- bus, devfn >> 3, devfn & 7, dev_path(dev));
- for(i = 0; i < 256; i++) {
- if ((i & 0x0f) == 0) {
- printk_info("%02x:", i);
- }
- printk_info(" %02x", pci_read_config8(dev, i));
- if ((i & 0x0f) == 0xf) {
- printk_info("\n");
- }
- }
- printk_info("\n");
- }
- }
-#endif
-#if 0
- msr_t msr;
- unsigned index;
- unsigned eax, ebx, ecx, edx;
- index = 0x80000007;
- printk_debug("calling cpuid 0x%08x\n", index);
- asm volatile(
- "cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (index)
- );
- printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
- index, eax, ebx, ecx, edx);
- if (edx & (3 << 1)) {
- index = 0xC0010042;
- printk_debug("Reading msr: 0x%08x\n", index);
- msr = rdmsr(index);
- printk_debug("msr[0x%08x]: 0x%08x%08x\n",
- index, msr.hi, msr.hi);
- }
-#endif
-}
-
-static void debug_noop(device_t dummy)
-{
-}
-
-static struct device_operations debug_operations = {
- .read_resources = debug_noop,
- .set_resources = debug_noop,
- .enable_resources = debug_noop,
- .init = debug_init,
-};
-
-static unsigned int scan_root_bus(device_t root, unsigned int max)
-{
- struct device_path path;
- device_t debug;
- max = root_dev_scan_bus(root, max);
- path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = 0;
- path.u.pnp.device = 0;
- debug = alloc_dev(&root->link[1], &path);
- debug->ops = &debug_operations;
- return max;
-}
-#endif
-
-static void mainboard_init(device_t dev)
-{
- root_dev_init(dev);
-
-// do_verify_cpu_voltages();
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = mainboard_init,
-#if !DEBUG
- .scan_bus = root_dev_scan_bus,
-#else
- .scan_bus = scan_root_bus,
-#endif
- .enable = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- dev_root.ops = &mainboard_operations;
-}
struct chip_operations mainboard_tyan_s4882_ops = {
- .enable_dev = enable_dev,
+ CHIP_NAME("Tyan s4882 mainboard")
};
diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
index 8438fcf23b..03277abaaf 100644
--- a/src/mainboard/via/epia-m/Config.lb
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -1,87 +1,3 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses HAVE_ACPI_TABLES
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default HAVE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=5
-object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
-
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
@@ -100,7 +16,6 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@@ -127,8 +42,8 @@ arch i386 end
## Build the objects we have code for in this directory.
##
-
driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if HAVE_ACPI_TABLES
@@ -140,41 +55,41 @@ end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -O -mcpu=c3 ./auto.E "
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
@@ -186,11 +101,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-# mainboardinit cpu/p6/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -208,7 +118,10 @@ end
##
## Setup RAM
##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -216,30 +129,24 @@ mainboardinit ./auto.inc
dir /pc80
config chip.h
-northbridge via/vt8623 "vt8623"
- southbridge via/vt8235 "vt8235"
- register "enable_usb" = "0"
- register "enable_native_ide" = "0"
- register "enable_com_ports" = "1"
- register "enable_keyboard" = "0"
- register "enable_nvram" = "1"
- end
- southbridge ricoh/rl5c476 "rl5c476"
- end
- superio via/vt1211 "vt1211"
- register "enable_com_ports" = "1"
- register "enable_hwmon" = "1"
- register "enable_lpt" = "1"
- register "enable_fdc" = "1"
+chip northbridge/via/vt8623
+ device pci_domain 0 on
+ chip southbridge/via/vt8235
+ register "enable_usb" = "0"
+ register "enable_native_ide" = "0"
+ register "enable_com_ports" = "1"
+ register "enable_keyboard" = "0"
+ register "enable_nvram" = "1"
+ end
+ chip southbridge/ricoh/rl5c476
+ end
+ chip superio/via/vt1211
+ register "enable_com_ports" = "1"
+ register "enable_hwmon" = "1"
+ register "enable_lpt" = "1"
+ register "enable_fdc" = "1"
+ end
+ chip cpu/via/model_centaur
+ end
end
end
-
-cpu p6 "cpu0"
-
-end
-
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c
index 6fbc8306a4..79dbb27867 100644
--- a/src/mainboard/via/epia-m/auto.c
+++ b/src/mainboard/via/epia-m/auto.c
@@ -3,7 +3,9 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <cpu/p6/apic.h>
+#if 0
+#include <cpu/x86/lapic.h>
+#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@@ -12,7 +14,8 @@
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/via/vt8623/raminit.h"
-#include "cpu/p6/earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
/*
*/
@@ -24,7 +27,7 @@ void udelay(int usecs)
}
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "debug.c"
#include "southbridge/via/vt8235/vt8235_early_smbus.c"
@@ -95,10 +98,22 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
-static void main(void)
+static void main(unsigned long bist)
{
unsigned long x;
device_t dev;
+
+ if (bist == 0) {
+ early_mtrr_init();
+ }
+ enable_vt8235_serial();
+ uart_init();
+ console_init();
+
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
/* init_timer();*/
outb(5, 0x80);
@@ -108,10 +123,7 @@ static void main(void)
outb(5, 0x80);
enable_smbus();
- enable_vt8235_serial();
- uart_init();
- console_init();
enable_mainboard_devices();
enable_shadow_ram();
@@ -144,5 +156,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
- early_mtrr_init();
}
diff --git a/src/mainboard/via/epia-m/chip.h b/src/mainboard/via/epia-m/chip.h
index 7b62d6d50b..2710e7b035 100644
--- a/src/mainboard/via/epia-m/chip.h
+++ b/src/mainboard/via/epia-m/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_via_epia_m_control;
+extern struct chip_operations mainboard_via_epia_m_ops;
struct mainboard_via_epia_m_config {
int nothing;
diff --git a/src/mainboard/via/epia-m/failover.c b/src/mainboard/via/epia-m/failover.c
index bd0df4e89d..bdcb9eaed2 100644
--- a/src/mainboard/via/epia-m/failover.c
+++ b/src/mainboard/via/epia-m/failover.c
@@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
-#include "cpu/p6/boot_cpu.c"
-static void main(void)
+static unsigned long main(unsigned long bist)
{
- /* for now, just always assume failure */
-
-#if 0
- /* Is this a cpu reset? */
- if (cpu_init_detected()) {
- if (last_boot_normal()) {
- asm("jmp __normal_image");
- } else {
- asm("jmp __cpu_reset");
- }
- }
-
/* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- asm("jmp __normal_image");
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
}
-#endif
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
}
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index a278af7fff..9eb7b3705b 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -3,24 +3,13 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
#include <arch/io.h>
#include "chip.h"
void vga_enable_console();
-static int
-mainboard_scan_bus(device_t root, int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-void vga_fixup(void) {
+static void vga_fixup(void) {
// we do this right here because:
// - all the hardware is working, and some VGA bioses seem to need
// that
@@ -36,7 +25,7 @@ void vga_fixup(void) {
}
-void write_protect_vgabios(void)
+static void write_protect_vgabios(void)
{
device_t dev;
@@ -44,25 +33,9 @@ void write_protect_vgabios(void)
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
if(dev)
pci_write_config8(dev, 0x61, 0xaa);
-
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
- .enable = 0,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainboard_operations;
}
-struct chip_operations mainboard_via_epia_m_control = {
- .enable_dev = enable_dev,
- .name = "VIA EPIA-M mainboard ",
+struct chip_operations mainboard_via_epia_m_ops = {
+ CHIP_NAME("VIA EPIA-M mainboard ")
};
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
index d8485dff0a..448d86fb09 100644
--- a/src/mainboard/via/epia/Config.lb
+++ b/src/mainboard/via/epia/Config.lb
@@ -42,7 +42,6 @@ arch i386 end
## Build the objects we have code for in this directory.
##
-
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
@@ -51,22 +50,22 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "./failover.E ./romcc"
- action "./romcc -O -mcpu=c3 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "./auto.E ./romcc"
- action "./romcc -O -mcpu=c3 ./auto.E "
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@@ -97,11 +96,6 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-##
-## Setup our mtrrs
-##
-# mainboardinit cpu/p6/earlymtrr.inc
-
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
@@ -119,7 +113,10 @@ end
##
## Setup RAM
##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
@@ -183,13 +180,6 @@ chip northbridge/via/vt8601
end
end
end
- chip cpu/via/model_centaur
+ chip cpu/via/model_centaur
end
end
-
-##
-## Include the old serial code for those few places that still need it.
-##
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-
diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c
index 377dc54754..6c8ea903ee 100644
--- a/src/mainboard/via/epia/auto.c
+++ b/src/mainboard/via/epia/auto.c
@@ -2,7 +2,9 @@
#include <stdint.h>
#include <device/pci_def.h>
+#if 0
#include <cpu/x86/lapic.h>
+#endif
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
@@ -12,6 +14,7 @@
#include "ram/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
/*
*/
@@ -93,14 +96,19 @@ static void enable_shadow_ram(void)
pci_write_config8(dev, 0x63, shadowreg);
}
-static void main(void)
+static void main(unsigned long bist)
{
unsigned long x;
+ if (bist == 0) {
+ early_mtrr_init();
+ }
enable_vt8231_serial();
-
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
enable_mainboard_devices();
enable_smbus();
@@ -134,5 +142,4 @@ static void main(void)
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
- early_mtrr_init();
}
diff --git a/src/mainboard/via/epia/failover.c b/src/mainboard/via/epia/failover.c
index 10bb2f48c1..bdcb9eaed2 100644
--- a/src/mainboard/via/epia/failover.c
+++ b/src/mainboard/via/epia/failover.c
@@ -5,25 +5,28 @@
#include <arch/io.h>
#include "arch/romcc_io.h"
#include "pc80/mc146818rtc_early.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-static void main(void)
+static unsigned long main(unsigned long bist)
{
- /* for now, just always assume failure */
-
-#if 0
- /* Is this a cpu reset? */
- if (cpu_init_detected()) {
- if (last_boot_normal()) {
- asm("jmp __normal_image");
- } else {
- asm("jmp __cpu_reset");
- }
- }
-
/* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- asm("jmp __normal_image");
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
}
-#endif
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
}
diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c
index bed59cd76e..9f3326a930 100644
--- a/src/mainboard/via/epia/mainboard.c
+++ b/src/mainboard/via/epia/mainboard.c
@@ -3,36 +3,10 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-
#include <arch/io.h>
#include "chip.h"
-static unsigned int
-mainboard_scan_bus(device_t root, unsigned int maxbus)
-{
- int retval;
- printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
- retval = pci_scan_bus(root->bus, 0, 0xff, maxbus);
- printk_spew("DONE %s: return %d\n", __FUNCTION__, maxbus);
- return maxbus;
-}
-
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = root_dev_enable_resources,
- .init = root_dev_init,
- .scan_bus = mainboard_scan_bus,
- .enable = 0,
-};
-
-static void enable_dev(device_t dev)
-{
- dev->ops = &mainboard_operations;
-}
-
struct chip_operations mainboard_via_epia_ops = {
- .enable_dev = enable_dev,
- .name = "VIA EPIA mainboard ",
+ CHIP_NAME("VIA EPIA mainboard ")
};