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authorChris Wang <chris.wang@amd.corp-partner.google.com>2018-11-05 21:51:55 +0800
committerMartin Roth <martinroth@google.com>2018-11-09 09:15:43 +0000
commit05b7cab1d7042d82e98387d6fc5849ff2d4df9db (patch)
treec896a1031aeb17dab241534e4780451e2be0a683 /src/mainboard
parent50c11607a1afaa373d381575c5056e4185a014c4 (diff)
downloadcoreboot-05b7cab1d7042d82e98387d6fc5849ff2d4df9db.tar.xz
mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 ms
Add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM. Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29473 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/variants/liara/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
index 343fbeb4dc..eef984a6d7 100644
--- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
@@ -20,6 +20,8 @@ chip soc/amd/stoneyridge
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
+ register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
+ register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{