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authorEric Biederman <ebiederm@xmission.com>2003-09-02 17:16:48 +0000
committerEric Biederman <ebiederm@xmission.com>2003-09-02 17:16:48 +0000
commit0ac6b41e70b2df365f8579c6e14214c42ab4c91b (patch)
tree40e26dbeec991f1df5e43da3e1ee9f25151b89d0 /src/mainboard
parente9a271e32c53076445ef70da8aec8201c82693ec (diff)
downloadcoreboot-0ac6b41e70b2df365f8579c6e14214c42ab4c91b.tar.xz
- 1.1.4
Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/arima/hdama/Config.lb13
-rw-r--r--src/mainboard/arima/hdama/mainboard.c35
-rw-r--r--src/mainboard/arima/hdama/mptable.c22
3 files changed, 39 insertions, 31 deletions
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index 80c3bfca11..824e43ff67 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -222,6 +222,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
## Include the secondary Configuration files
##
dir /pc80
+config chip.h
northbridge amd/amdk8 "mc0"
pci 0:18.0
@@ -263,12 +264,12 @@ northbridge amd/amdk8 "mc0"
end
northbridge amd/amdk8 "mc1"
- #pci 0:19.0
- #pci 0:19.0
- #pci 0:19.0
- #pci 0:19.1
- #pci 0:19.2
- #pci 0:19.3
+ pci 0:19.0
+ pci 0:19.0
+ pci 0:19.0
+ pci 0:19.1
+ pci 0:19.2
+ pci 0:19.3
end
cpu k8 "cpu0"
diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c
index 4f40e393b2..c5812ece3f 100644
--- a/src/mainboard/arima/hdama/mainboard.c
+++ b/src/mainboard/arima/hdama/mainboard.c
@@ -1,3 +1,4 @@
+
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -6,6 +7,7 @@
#include <arch/io.h>
#include <device/chip.h>
+#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
@@ -14,22 +16,27 @@ unsigned long initial_apicid[CONFIG_MAX_CPUS] =
0, 1,
};
-static void
-enable(struct chip *chip, enum chip_pass pass)
-{
-
- struct mainboard_arima_hdama_config *conf =
- (struct mainboard_arima_hdama_config *)chip->chip_info;
-
- switch (pass) {
- default: break;
- case CONF_PASS_PRE_BOOT:
- break;
- }
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = enable_childrens_resources,
+ .init = 0,
+ .scan_bus = amdk8_scan_root_bus,
+ .enable = 0,
+};
+static void enumerate(struct chip *chip)
+{
+ struct chip *child;
+ dev_root.ops = &mainboard_operations;
+ chip->dev = &dev_root;
+ chip->bus = 0;
+ for(child = chip->children; child; child = child->next) {
+ child->bus = &dev_root.link[0];
+ }
}
struct chip_control mainboard_arima_hdama_control = {
- enable: enable,
- name: "Arima HDAMA mainboard "
+ .enumerate = enumerate,
+ .name = "Arima HDAMA mainboard ",
};
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 856288590d..94ac735744 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -36,40 +36,40 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_processors(mc, processor_map);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+
/* 8111 */
- dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
+ dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
- printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n");
+ printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 3;
bus_isa = 4;
}
/* 8131-1 */
- dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n");
+ printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 1;
}
/* 8131-2 */
- dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
- printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n");
+ printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 2;
}
@@ -85,17 +85,17 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
+ device_t dev;
uint32_t base;
/* 8131 apic 3 */
- dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base);
}
/* 8131 apic 4 */
- dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK;