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authorVadim Bendebury <vbendeb@chromium.org>2016-06-21 19:07:32 -0700
committerMartin Roth <martinroth@google.com>2016-07-10 03:53:57 +0200
commit1f83ffac1b30e7b6ed59fb26ee2ba57cec4938eb (patch)
tree22977f9c7f7e65f1bd09ba6469f73ff8dc580ec8 /src/mainboard
parent9ae0985328d53b0a2b1a6673853367061dd695cd (diff)
downloadcoreboot-1f83ffac1b30e7b6ed59fb26ee2ba57cec4938eb.tar.xz
gru: include ram_code in coreboot table
This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15566 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/gru/Kconfig1
-rw-r--r--src/mainboard/google/gru/Makefile.inc1
-rw-r--r--src/mainboard/google/gru/boardid.c5
-rw-r--r--src/mainboard/google/gru/sdram_configs.c22
4 files changed, 18 insertions, 11 deletions
diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig
index 170e358bda..1b42059032 100644
--- a/src/mainboard/google/gru/Kconfig
+++ b/src/mainboard/google/gru/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_DO_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select RAM_CODE_SUPPORT
select RTC
select SOC_ROCKCHIP_RK3399
select SPI_FLASH
diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc
index a209d1bdf3..9e87fadd1c 100644
--- a/src/mainboard/google/gru/Makefile.inc
+++ b/src/mainboard/google/gru/Makefile.inc
@@ -33,3 +33,4 @@ ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
+ramstage-y += sdram_configs.c # Needed for ram_code()
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 1d37a867a8..b0c1eaf17e 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -59,8 +59,3 @@ uint8_t board_id(void)
adc_reading);
return 0;
}
-
-uint32_t ram_code(void)
-{
- return 0;
-}
diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c
index 92e00efdba..f1f889c334 100644
--- a/src/mainboard/google/gru/sdram_configs.c
+++ b/src/mainboard/google/gru/sdram_configs.c
@@ -38,19 +38,29 @@ enum dram_speeds {
/* dram_928MHz = 4, */
};
-const struct rk3399_sdram_params *get_sdram_config()
+static enum dram_speeds get_sdram_index(void)
{
- enum dram_speeds speed;
-
if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
- speed = dram_300MHz;
+ return dram_300MHz;
else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
- speed = dram_800MHz;
+ return dram_800MHz;
else
- speed = dram_200MHz;
+ return dram_200MHz;
+}
+
+const struct rk3399_sdram_params *get_sdram_config()
+{
+
+ enum dram_speeds speed = get_sdram_index();
printk(BIOS_INFO, "Using SDRAM configuration for %d MHz\n",
sdram_configs[speed].ddr_freq / (1000 * 1000));
return &sdram_configs[speed];
}
+
+
+uint32_t ram_code(void)
+{
+ return get_sdram_index();
+}