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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/mainboard
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
downloadcoreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/cubietech/cubieboard/bootblock.c14
-rw-r--r--src/mainboard/google/nyan/bootblock.c2
-rw-r--r--src/mainboard/google/nyan/mainboard.c8
-rw-r--r--src/mainboard/google/nyan_big/bootblock.c2
-rw-r--r--src/mainboard/google/nyan_big/mainboard.c8
-rw-r--r--src/mainboard/google/nyan_blaze/bootblock.c2
-rw-r--r--src/mainboard/google/nyan_blaze/mainboard.c8
-rw-r--r--src/mainboard/google/peach_pit/mainboard.c4
-rw-r--r--src/mainboard/google/rush/bootblock.c2
-rw-r--r--src/mainboard/google/rush_ryu/bootblock.c2
-rw-r--r--src/mainboard/google/storm/reset.c12
-rw-r--r--src/mainboard/google/veyron_brain/bootblock.c8
-rw-r--r--src/mainboard/google/veyron_brain/mainboard.c18
-rw-r--r--src/mainboard/google/veyron_brain/romstage.c2
-rw-r--r--src/mainboard/google/veyron_danger/bootblock.c8
-rw-r--r--src/mainboard/google/veyron_danger/mainboard.c22
-rw-r--r--src/mainboard/google/veyron_danger/romstage.c2
-rw-r--r--src/mainboard/google/veyron_jerry/bootblock.c10
-rw-r--r--src/mainboard/google/veyron_jerry/mainboard.c24
-rw-r--r--src/mainboard/google/veyron_jerry/romstage.c2
-rw-r--r--src/mainboard/google/veyron_mighty/bootblock.c10
-rw-r--r--src/mainboard/google/veyron_mighty/mainboard.c24
-rw-r--r--src/mainboard/google/veyron_mighty/romstage.c2
-rw-r--r--src/mainboard/google/veyron_pinky/bootblock.c10
-rw-r--r--src/mainboard/google/veyron_pinky/mainboard.c24
-rw-r--r--src/mainboard/google/veyron_pinky/romstage.c2
-rw-r--r--src/mainboard/google/veyron_rialto/bootblock.c8
-rw-r--r--src/mainboard/google/veyron_rialto/mainboard.c14
-rw-r--r--src/mainboard/google/veyron_rialto/romstage.c2
-rw-r--r--src/mainboard/google/veyron_speedy/bootblock.c10
-rw-r--r--src/mainboard/google/veyron_speedy/mainboard.c24
-rw-r--r--src/mainboard/google/veyron_speedy/romstage.c2
-rw-r--r--src/mainboard/ti/beaglebone/bootblock.c4
33 files changed, 148 insertions, 148 deletions
diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c
index 79d00189e8..e4a0313bd4 100644
--- a/src/mainboard/cubietech/cubieboard/bootblock.c
+++ b/src/mainboard/cubietech/cubieboard/bootblock.c
@@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void)
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
/* Switch CPU clock to main oscillator */
- writel(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
/* Configure the PLL1. The value is the same one used by u-boot
* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
*/
- writel(0xa1005000, &ccm->pll1_cfg);
+ write32(&ccm->pll1_cfg, 0xa1005000);
/* FIXME: Delay to wait for PLL to lock */
u32 wait = 1000;
@@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= CPU_CLK_SRC_PLL1;
- writel(reg32, &ccm->cpu_ahb_apb0_cfg);
+ write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void cubieboard_setup_clocks(void)
@@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void)
cubieboard_set_sys_clock();
/* Configure the clock source for APB1. This drives our UART */
- writel(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
- &ccm->apb1_clk_div_cfg);
+ write32(&ccm->apb1_clk_div_cfg,
+ APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
/* Configure the clock for SD0 */
- writel(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1),
- &ccm->sd0_clk_cfg);
+ write32(&ccm->sd0_clk_cfg,
+ SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index bc3cd3efa2..9e26e296f3 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -36,7 +36,7 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+ write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
clock_configure_source(mselect, PLLP, 102000);
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index dce4cbcbd5..97ae227c2d 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -184,13 +184,13 @@ static void setup_kernel_info(void)
// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
- writel(0x80080000, &pmc->odmdata);
+ write32(&pmc->odmdata, 0x80080000);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
- writel(0, &mc->video_protect_bom);
- writel(0, &mc->video_protect_size_mb);
- writel(1, &mc->video_protect_reg_ctrl);
+ write32(&mc->video_protect_bom, 0);
+ write32(&mc->video_protect_size_mb, 0);
+ write32(&mc->video_protect_reg_ctrl, 1);
}
static void setup_ec_spi(void)
diff --git a/src/mainboard/google/nyan_big/bootblock.c b/src/mainboard/google/nyan_big/bootblock.c
index c471cb841a..94943974d1 100644
--- a/src/mainboard/google/nyan_big/bootblock.c
+++ b/src/mainboard/google/nyan_big/bootblock.c
@@ -36,7 +36,7 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+ write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
clock_configure_source(mselect, PLLP, 102000);
diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c
index 712269a708..f899dab3fb 100644
--- a/src/mainboard/google/nyan_big/mainboard.c
+++ b/src/mainboard/google/nyan_big/mainboard.c
@@ -184,13 +184,13 @@ static void setup_kernel_info(void)
// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
- writel(0x80080000, &pmc->odmdata);
+ write32(&pmc->odmdata, 0x80080000);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
- writel(0, &mc->video_protect_bom);
- writel(0, &mc->video_protect_size_mb);
- writel(1, &mc->video_protect_reg_ctrl);
+ write32(&mc->video_protect_bom, 0);
+ write32(&mc->video_protect_size_mb, 0);
+ write32(&mc->video_protect_reg_ctrl, 1);
}
static void setup_ec_spi(void)
diff --git a/src/mainboard/google/nyan_blaze/bootblock.c b/src/mainboard/google/nyan_blaze/bootblock.c
index c471cb841a..94943974d1 100644
--- a/src/mainboard/google/nyan_blaze/bootblock.c
+++ b/src/mainboard/google/nyan_blaze/bootblock.c
@@ -36,7 +36,7 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
+ write32(&clk_rst->clk_src_uarta, PLLP << CLK_SOURCE_SHIFT);
clock_configure_source(mselect, PLLP, 102000);
diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c
index 9daa2bb6b3..f5aa1393f1 100644
--- a/src/mainboard/google/nyan_blaze/mainboard.c
+++ b/src/mainboard/google/nyan_blaze/mainboard.c
@@ -184,13 +184,13 @@ static void setup_kernel_info(void)
// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
- writel(0x80080000, &pmc->odmdata);
+ write32(&pmc->odmdata, 0x80080000);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
- writel(0, &mc->video_protect_bom);
- writel(0, &mc->video_protect_size_mb);
- writel(1, &mc->video_protect_reg_ctrl);
+ write32(&mc->video_protect_bom, 0);
+ write32(&mc->video_protect_size_mb, 0);
+ write32(&mc->video_protect_reg_ctrl, 1);
}
static void setup_ec_spi(void)
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index fb37cde6d4..ff2ef86056 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -429,8 +429,8 @@ static void mainboard_init(device_t dev)
* been found to come up as 3. This means FIMD SYSMMU is on by
* default on Exynos5420. For now we are disabling FIMD SYSMMU.
*/
- writel(0x0, (void *)0x14640000);
- writel(0x0, (void *)0x14680000);
+ write32((void *)0x14640000, 0x0);
+ write32((void *)0x14680000, 0x0);
lcd_vdd();
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c
index 2d099fb6c3..13d1f6726e 100644
--- a/src/mainboard/google/rush/bootblock.c
+++ b/src/mainboard/google/rush/bootblock.c
@@ -85,7 +85,7 @@ void bootblock_mainboard_early_init(void)
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, CLK_RST_REG(clk_src_uarta));
+ write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
}
void bootblock_mainboard_init(void)
diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c
index 2272ce1370..232baafbc9 100644
--- a/src/mainboard/google/rush_ryu/bootblock.c
+++ b/src/mainboard/google/rush_ryu/bootblock.c
@@ -71,7 +71,7 @@ void bootblock_mainboard_early_init(void)
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
- writel(PLLP << CLK_SOURCE_SHIFT, CLK_RST_REG(clk_src_uarta));
+ write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
}
static const struct pad_config padcfgs[] = {
diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c
index 58c52f91d9..0bac9cc7dc 100644
--- a/src/mainboard/google/storm/reset.c
+++ b/src/mainboard/google/storm/reset.c
@@ -35,12 +35,12 @@ static void wdog_reset(void)
{
printk(BIOS_DEBUG, "\nResetting with watchdog!\n");
- writel(0, APCS_WDT0_EN);
- writel(1, APCS_WDT0_RST);
- writel(RESET_WDT_BARK_TIME, APCS_WDT0_BARK_TIME);
- writel(RESET_WDT_BITE_TIME, APCS_WDT0_BITE_TIME);
- writel(1, APCS_WDT0_EN);
- writel(1, APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE);
+ write32(APCS_WDT0_EN, 0);
+ write32(APCS_WDT0_RST, 1);
+ write32(APCS_WDT0_BARK_TIME, RESET_WDT_BARK_TIME);
+ write32(APCS_WDT0_BITE_TIME, RESET_WDT_BITE_TIME);
+ write32(APCS_WDT0_EN, 1);
+ write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1);
for (;;)
;
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index 68234c9609..678059f954 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -64,12 +64,12 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_brain/mainboard.c b/src/mainboard/google/veyron_brain/mainboard.c
index 8e2bbb61e3..45873b68b3 100644
--- a/src/mainboard/google/veyron_brain/mainboard.c
+++ b/src/mainboard/google/veyron_brain/mainboard.c
@@ -50,34 +50,34 @@ static void configure_usb(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
index 37efcaac6b..4156401cc0 100644
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ b/src/mainboard/google/veyron_brain/romstage.c
@@ -48,7 +48,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index 68234c9609..678059f954 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -64,12 +64,12 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_danger/mainboard.c b/src/mainboard/google/veyron_danger/mainboard.c
index 8f01783157..b664d55804 100644
--- a/src/mainboard/google/veyron_danger/mainboard.c
+++ b/src/mainboard/google/veyron_danger/mainboard.c
@@ -50,10 +50,10 @@ static void configure_usb(void)
static void configure_sdmmc(void)
{
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
@@ -64,34 +64,34 @@ static void configure_sdmmc(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
index f3883bd28f..9be13fe894 100644
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ b/src/mainboard/google/veyron_danger/romstage.c
@@ -49,7 +49,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 19c2aec0db..985152bebc 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -62,16 +62,16 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
index 1fc823c5fe..6fb3a8f6ea 100644
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ b/src/mainboard/google/veyron_jerry/mainboard.c
@@ -50,10 +50,10 @@ static void configure_usb(void)
static void configure_sdmmc(void)
{
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
@@ -64,34 +64,34 @@ static void configure_sdmmc(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 2:
@@ -107,7 +107,7 @@ static void configure_vop(void)
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
- writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
+ write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c
index 9d19586cd5..e8f54deedd 100644
--- a/src/mainboard/google/veyron_jerry/romstage.c
+++ b/src/mainboard/google/veyron_jerry/romstage.c
@@ -48,7 +48,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 19c2aec0db..985152bebc 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -62,16 +62,16 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
index fb1d8fa69e..5c417544ea 100644
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ b/src/mainboard/google/veyron_mighty/mainboard.c
@@ -50,10 +50,10 @@ static void configure_usb(void)
static void configure_sdmmc(void)
{
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
@@ -64,34 +64,34 @@ static void configure_sdmmc(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 0:
@@ -107,7 +107,7 @@ static void configure_vop(void)
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
- writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
+ write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c
index 9d19586cd5..e8f54deedd 100644
--- a/src/mainboard/google/veyron_mighty/romstage.c
+++ b/src/mainboard/google/veyron_mighty/romstage.c
@@ -48,7 +48,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 19c2aec0db..985152bebc 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -62,16 +62,16 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index e3e5b290a9..ef14c2d6b1 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -60,10 +60,10 @@ static void configure_usb(void)
static void configure_sdmmc(void)
{
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
switch (board_id()) {
@@ -82,9 +82,9 @@ static void configure_sdmmc(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
switch (board_id()) {
case 0:
@@ -104,11 +104,11 @@ static void configure_emmc(void)
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
switch (board_id()) {
case 0:
@@ -120,16 +120,16 @@ static void configure_codec(void)
}
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 0:
@@ -151,7 +151,7 @@ static void configure_vop(void)
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
- writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
+ write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c
index 74c5ef3585..3e885647c7 100644
--- a/src/mainboard/google/veyron_pinky/romstage.c
+++ b/src/mainboard/google/veyron_pinky/romstage.c
@@ -48,7 +48,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index ab9d60dad0..135aece472 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -62,12 +62,12 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c
index d03a917c09..eb6efd3290 100644
--- a/src/mainboard/google/veyron_rialto/mainboard.c
+++ b/src/mainboard/google/veyron_rialto/mainboard.c
@@ -50,25 +50,25 @@ static void configure_usb(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index f3883bd28f..9be13fe894 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -49,7 +49,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 19c2aec0db..985152bebc 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -38,7 +38,7 @@ void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
@@ -62,16 +62,16 @@ void bootblock_mainboard_init(void)
rkclk_configure_cpu();
/* i2c1 for tpm */
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
+ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
+ write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
+ write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
/* spi0 for chrome ec */
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
+ write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
setup_chromeos_gpios();
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
index fb1d8fa69e..5c417544ea 100644
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ b/src/mainboard/google/veyron_speedy/mainboard.c
@@ -50,10 +50,10 @@ static void configure_usb(void)
static void configure_sdmmc(void)
{
- writel(IOMUX_SDMMC0, &rk3288_grf->iomux_sdmmc0);
+ write32(&rk3288_grf->iomux_sdmmc0, IOMUX_SDMMC0);
/* use sdmmc0 io, disable JTAG function */
- writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
+ write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << 12));
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
@@ -64,34 +64,34 @@ static void configure_sdmmc(void)
static void configure_emmc(void)
{
- writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata);
- writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren);
- writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd);
+ write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
+ write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
+ write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
- writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */
+ write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
- writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
- writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
+ write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
+ write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
- writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
- writel(IOMUX_LCDC, &rk3288_grf->iomux_lcdc);
+ write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
- writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
+ write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
switch (board_id()) {
case 0:
@@ -107,7 +107,7 @@ static void configure_vop(void)
/* enable edp HPD */
gpio_input_pulldown(GPIO(7, B, 3));
- writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
+ write32(&rk3288_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG);
break;
}
}
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c
index f3883bd28f..9be13fe894 100644
--- a/src/mainboard/google/veyron_speedy/romstage.c
+++ b/src/mainboard/google/veyron_speedy/romstage.c
@@ -49,7 +49,7 @@ static void regulate_vdd_log(unsigned int mv)
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
- writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1);
+ write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c
index 2b22227fb2..3144eddb27 100644
--- a/src/mainboard/ti/beaglebone/bootblock.c
+++ b/src/mainboard/ti/beaglebone/bootblock.c
@@ -29,7 +29,7 @@ void bootblock_mainboard_init(void)
void *uart_clock_ctrl = NULL;
/* Enable the GPIO module */
- writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac));
+ write32((uint32_t *)(0x44e00000 + 0xac), (0x2 << 0) | (1 << 18));
/* Disable interrupts from these GPIOs */
setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21);
@@ -62,7 +62,7 @@ void bootblock_mainboard_init(void)
uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38);
}
if (uart_clock_ctrl)
- writel(0x2, uart_clock_ctrl);
+ write32(uart_clock_ctrl, 0x2);
/* Start monotonic timer */
//rtc_start();