summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2016-11-14 00:05:29 +0100
committerMartin Roth <martinroth@google.com>2016-11-16 18:10:14 +0100
commit37d15c6cab5aca9de39377cb5018c35537676faa (patch)
tree17f7888bf7fb0dca8161addbeb0ac524081c44a9 /src/mainboard
parent28726d1cec9f45b03f950c02adcf8d52555d3b73 (diff)
downloadcoreboot-37d15c6cab5aca9de39377cb5018c35537676faa.tar.xz
mb/ga-945gcm-s2l: Clean up Superio
GPIO register at offset 0xfc (VID Input Register) is read-only but writing 1 to bit 0 will update initial VID input. Change-Id: Ie372e98f8e497eede382975262a63d58c16227b9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17412 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index d83ab745b1..e60442eba1 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -66,8 +66,7 @@ static void setup_sio(void)
ite_reg_write(GPIO_DEV, 0x29, 0x88);
ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
ite_reg_write(GPIO_DEV, 0x62, 0x08);
- ite_reg_write(GPIO_DEV, 0x72, 0x00);
- ite_reg_write(GPIO_DEV, 0x73, 0x38);
+ ite_kill_watchdog(GPIO_DEV);
ite_reg_write(GPIO_DEV, 0xb1, 0x01);
ite_reg_write(GPIO_DEV, 0xb8, 0x80);
ite_reg_write(GPIO_DEV, 0xbb, 0x40);
@@ -76,7 +75,7 @@ static void setup_sio(void)
ite_reg_write(GPIO_DEV, 0xc8, 0x00);
ite_reg_write(GPIO_DEV, 0xcb, 0x00);
ite_reg_write(GPIO_DEV, 0xf6, 0x26);
- ite_reg_write(GPIO_DEV, 0xfc, 0x4a);
+ ite_reg_write(GPIO_DEV, 0xfc, 0x01);
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
ite_reg_write(EC_DEV, 0x30, 0xff); // Enable