diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-11 14:55:47 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:39:38 +0200 |
| commit | 3fbf671194a8f1469bf0e122fed8e8da23893ac9 (patch) | |
| tree | cfeab76a7fed7f75c5170a69f3eee68072ddc28c /src/mainboard | |
| parent | 9f83e873f4f0a06a68f68414720e837a69f54184 (diff) | |
| download | coreboot-3fbf671194a8f1469bf0e122fed8e8da23893ac9.tar.xz | |
rambi: mainboard EC - SCI and SMI fixes
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
'lidclose' on EC console while at recovery screen. Machine properly
shutdown.
Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
Reviewed-on: http://review.coreboot.org/4959
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/rambi/ec.c | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rambi/mainboard_smi.c | 13 |
2 files changed, 11 insertions, 3 deletions
diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 04a9931020..a6d21618a8 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -42,6 +42,7 @@ void mainboard_ec_init(void) } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S5_WAKE_EVENTS); + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); } /* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index ac5c841030..09a858039d 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -28,6 +28,9 @@ #include <baytrail/nvs.h> #include <baytrail/pmc.h> +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + int mainboard_io_trap_handler(int smif) { switch (smif) { @@ -67,7 +70,7 @@ static uint8_t mainboard_smi_ec(void) /* Go to S5 */ pm1_cnt = inl(pmbase + PM1_CNT); - pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); outl(pm1_cnt, pmbase + PM1_CNT); break; } @@ -75,9 +78,11 @@ static uint8_t mainboard_smi_ec(void) return cmd; } -void mainboard_smi_gpi(uint32_t gpi_sts) +/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) { - if (gpi_sts & (1 << EC_SMI_GPI)) { + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0); } @@ -97,6 +102,8 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); break; case 5: if (smm_get_gnvs()->s5u0 == 0) |