summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorGreg Watson <jarrah@users.sourceforge.net>2004-01-22 01:06:19 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-01-22 01:06:19 +0000
commit5a8d4ae27cbcc7b6de3cd54770d51ffa6707dd6e (patch)
tree18720eddeea84c5252763efee61457df3ddf889d /src/mainboard
parent909472367fe4bbc91c43c0d8c4d9acb10d95e737 (diff)
downloadcoreboot-5a8d4ae27cbcc7b6de3cd54770d51ffa6707dd6e.tar.xz
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/totalimpact/briq/Config.lb14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index b59f873c6b..74a36eb3ab 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -4,20 +4,26 @@
uses PCIC0_CFGADDR
uses PCIC0_CFGDATA
-uses UART0_IO_BASE
+uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
##
## Set PCI registers
##
-default PCIC0_CFGADDR=0xeec00000
-default PCIC0_CFGDATA=0xeec00004
+default PCIC0_CFGADDR=0xff508000
+default PCIC0_CFGDATA=0xff508010
+
+##
+## Set IDE control registers
+##
+default PNP_CFGADDR=0x1f0
+default PNP_CFGDATA=0x1f1
##
## Set UART base address
##
-default UART0_IO_BASE=0xef600300
+default TTYS0_BASE=0x3f8
##
## Early board initialization, called from ppc_main()