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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-01-10 16:33:18 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-23 09:37:16 +0000
commit6ebb7394f97a387e0503b7b4035647f2d5df331f (patch)
treed3cb3983917b9e577875d63d1f3e7c19e3deacbf /src/mainboard
parent12b86b6433a9707580c485067e2ceba83e513417 (diff)
downloadcoreboot-6ebb7394f97a387e0503b7b4035647f2d5df331f.tar.xz
mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entries
Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/pcengines/apu1/buildOpts.c2
-rw-r--r--src/mainboard/pcengines/apu1/mainboard.c93
2 files changed, 94 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c
index 2b73fb1dcb..f2e4ab5fe2 100644
--- a/src/mainboard/pcengines/apu1/buildOpts.c
+++ b/src/mainboard/pcengines/apu1/buildOpts.c
@@ -87,7 +87,7 @@
#define BLDOPT_REMOVE_SRAT FALSE
#define BLDOPT_REMOVE_SLIT FALSE
#define BLDOPT_REMOVE_WHEA FALSE
-#define BLDOPT_REMOVE_DMI TRUE
+#define BLDOPT_REMOVE_DMI FALSE
#define BLDOPT_REMOVE_HT_ASSIST TRUE
#define BLDOPT_REMOVE_ATM_MODE TRUE
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 14eab8b490..d72a8fbcef 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -13,6 +13,8 @@
*/
#include <amdblocks/acpimmio.h>
+#include <AGESA.h>
+#include <AMD.h>
#include <console/console.h>
#include <device/device.h>
#include <device/mmio.h>
@@ -23,6 +25,7 @@
#include <string.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <southbridge/amd/cimx/sb800/pci_devs.h>
+#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/family14/pci_devs.h>
#include <superio/nuvoton/nct5104d/nct5104d.h>
#include "gpio_ftns.h"
@@ -173,6 +176,93 @@ static void config_addon_uart(void)
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, unsigned long *current)
+{
+ struct smbios_type16 *t;
+ u32 max_capacity;
+ int len;
+
+ t = (struct smbios_type16 *)*current;
+ len = sizeof(struct smbios_type16);
+ memset(t, 0, len);
+ max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */
+
+ t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+ t->handle = *handle;
+ t->length = len - 2;
+ t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+ t->use = MEMORY_ARRAY_USE_SYSTEM;
+ t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
+ t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection;
+ t->maximum_capacity = max_capacity * 1024 * 1024;
+ t->memory_error_information_handle = 0xfffe;
+ t->number_of_memory_devices = 1;
+
+ *current += len;
+
+ return len;
+}
+
+static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, unsigned long *current)
+{
+ struct smbios_type17 *t;
+ int len;
+
+ t = (struct smbios_type17 *)*current;
+ memset(t, 0, sizeof(struct smbios_type17));
+
+ t->type = SMBIOS_MEMORY_DEVICE;
+ t->length = sizeof(struct smbios_type17) - 2;
+ t->handle = *handle + 1;
+ t->phys_memory_array_handle = *handle;
+ t->memory_error_information_handle = 0xfffe;
+ t->total_width = agesa_dmi->T17[0][0][0].TotalWidth;
+ t->data_width = agesa_dmi->T17[0][0][0].DataWidth;
+ t->size = agesa_dmi->T17[0][0][0].MemorySize;
+ /* AGESA DMI returns form factor = 0, override it with SPD value */
+ t->form_factor = MEMORY_FORMFACTOR_SODIMM;
+ t->device_set = agesa_dmi->T17[0][0][0].DeviceSet;
+ t->device_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].DeviceLocator);
+ t->bank_locator = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].BankLocator);
+ t->memory_type = agesa_dmi->T17[0][0][0].MemoryType;
+ t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail;
+ t->speed = agesa_dmi->T17[0][0][0].Speed;
+ t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode;
+ t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber);
+ t->part_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].PartNumber);
+ t->attributes = agesa_dmi->T17[0][0][0].Attributes;
+ t->extended_size = agesa_dmi->T17[0][0][0].ExtSize;
+ t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed;
+ t->minimum_voltage = 1500; /* From SPD: 1.5V */
+ t->maximum_voltage = 1500;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+
+ return len;
+}
+
+static int mainboard_smbios_data(struct device *dev, int *handle,
+ unsigned long *current)
+{
+ DMI_INFO *agesa_dmi;
+ int len;
+
+ agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI);
+
+ if (!agesa_dmi)
+ return 0;
+
+ len = mainboard_smbios_type16(agesa_dmi, handle, current);
+ len += mainboard_smbios_type17(agesa_dmi, handle, current);
+
+ *handle += 2;
+
+ return len;
+}
+#endif
+
static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -194,6 +284,9 @@ static void mainboard_enable(struct device *dev)
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+#endif
}
/*