summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorVaradarajan Narayanan <varada@codeaurora.org>2016-01-06 14:13:25 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-05-10 23:24:08 +0200
commit6fbc763b816633653810e8b1a745b375fa9606c8 (patch)
treeababae59edd784a8320536f1eacda69b1d4bbd22 /src/mainboard
parent2596764f34a03e4f53704ca5efef71de5c4f9f4c (diff)
downloadcoreboot-6fbc763b816633653810e8b1a745b375fa9606c8.tar.xz
soc/qualcomm/ipq40xx: Enable crashdump handling
Clear the crash dump cookie set by SBL to indicate that it is a normal reset. Inform DDR image of the entrypoint for SDI image to be preserved in OCIMEM which will be needed during watchdog resets. BUG=chrome-os-partner:49249 TEST=DDR image is able to fetch the entry point address BRANCH=none Change-Id: I3e6e4a108585bb257e3ad02956c420acbcb2554e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd726256a5ae89672810b57e1d2a7a9287f60627 Original-Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333321 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14679 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/gale/reset.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c
index 47a46d42e9..d37051a9cb 100644
--- a/src/mainboard/google/gale/reset.c
+++ b/src/mainboard/google/gale/reset.c
@@ -21,5 +21,12 @@
void hard_reset(void)
{
+ /*
+ * At boot time the boot loaders would have set a magic cookie
+ * here to detect watchdog reset. However, since this is a
+ * normal reset clear the magic numbers.
+ */
+ write32(TCSR_BOOT_MISC_DETECT, 0);
+ write32(TCSR_RESET_DEBUG_SW_ENTRY, 0);
write32(GCNT_PSHOLD, 0);
}