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authorDeepika Punyamurtula <deepika.punyamurtula@intel.com>2020-06-09 08:21:02 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-06-11 16:15:41 +0000
commit92c779200aa4ae27ee8e986aca4615d12b6acbac (patch)
tree8b03bd4c7bea8bbb8298b403364233b2a26ffb78 /src/mainboard
parent91844b1f358e3ed3f043ee7c6f53ba8f4567a088 (diff)
downloadcoreboot-92c779200aa4ae27ee8e986aca4615d12b6acbac.tar.xz
mb/google/volteer: Update DPTF TSR2 sensor ID for volteer
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to report the same temperature under /sys/class/thermal and also swap TSR0 and TSR1 in DTRT to match physical sensor in volteer schematics BRANCH=None BUG=b:149722146 TEST=On volteer system check TSR1 and TSR2 temperatures, should report different values `cat /sys/class/thermal/thermal_zone[3,4]/temp` Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp` and `ectool tempsinfo all ; ectool temps all` Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl
index cef895b59f..2e59e5e395 100644
--- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -28,7 +28,7 @@
#define DPTF_TSR1_ACTIVE_AC3 42
#define DPTF_TSR1_ACTIVE_AC4 39
-#define DPTF_TSR2_SENSOR_ID 1
+#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3"
#define DPTF_TSR2_PASSIVE 65
#define DPTF_TSR2_CRITICAL 75
@@ -99,11 +99,11 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
- /* CPU Throttle Effect on TSR0 sensor */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+ /* CPU Throttle Effect on TSR1 sensor */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
- /* Charger Throttle Effect on Charger (TSR1) */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+ /* Charger Throttle Effect on Charger (TSR0) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR2 sensor */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },