diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-15 23:49:52 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:45:47 +0000 |
| commit | 934f683078f736e5409fcef749bf6f27774252c0 (patch) | |
| tree | 90b4752b797fae2aa92b0748c59ad02d5df3b96f /src/mainboard | |
| parent | 09b9b1673fdc5e4650a1f9499229c3fa338a7bab (diff) | |
| download | coreboot-934f683078f736e5409fcef749bf6f27774252c0.tar.xz | |
mb/asrock/b85m_pro4: Correct GP01 output level
This allows the CPU fan tach signal to reach the Super I/O.
Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index cb7df0a147..a5c275d427 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -79,7 +79,7 @@ chip northbridge/intel/haswell device pnp 2e.8 off end # WDT device pnp 2e.108 on # GPIO0 irq 0xe0 = 0xf9 # + GPIO0 direction - irq 0xe1 = 0xfb # + GPIO0 value + irq 0xe1 = 0xfd # + GPIO0 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base |