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| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-10-26 19:02:44 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-10-26 21:55:38 +0200 |
| commit | 95c607feadf6325c90842fec8fa64a2b32208295 (patch) | |
| tree | 88b8a7373fb8dc6be8c616b46081c49b00f8caaf /src/mainboard | |
| parent | 3e9155dddf4a439703f7b762648eb820307dbfe4 (diff) | |
| download | coreboot-95c607feadf6325c90842fec8fa64a2b32208295.tar.xz | |
iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
The PCI registers should be accessed aligned and 0x62 is not 32bit
aligned therefore this patch changes it to a 16bit access.
Change-Id: I00725a4569f471eedb061834f626911b42e734fb
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1631
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/iwave/iWRainbowG6/romstage.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 833d9301c7..83ae657430 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -321,11 +321,11 @@ static void poulsbo_setup_Stage1Regs(void) static void poulsbo_setup_Stage2Regs(void) { - u32 reg32; + u16 reg16; printk(BIOS_DEBUG, "Reserved"); - reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62); - pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); + reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62); + pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3)); /* Slot capabilities */ pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500); pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500); |