diff options
| author | Evan Green <evgreen@chromium.org> | 2019-03-18 09:08:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-22 12:17:37 +0000 |
| commit | 9c8044bdcd2aa77d8a8092b270ca36fd3aa23b87 (patch) | |
| tree | b6b499f301ec001852f214977b644bd097d5a5c8 /src/mainboard | |
| parent | 0146bce26252fa9e959c083fd69c8f667746de86 (diff) | |
| download | coreboot-9c8044bdcd2aa77d8a8092b270ca36fd3aa23b87.tar.xz | |
mb/google/hatch: Add SX9310 SAR0 sensor
Add SAR0, which is an SX9310. The schematics and layout have a second
SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this
is not populated.
Signed-off-by: Evan Green <evgreen@chromium.org>
BUG=b:128540461
BRANCH=none
TEST=Boot kernel with sx9310 driver, see it come up happily
Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 33 |
2 files changed, 33 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 629b125d93..f632a02d03 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -5,6 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9310 select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 0299ded7b5..2b18b3b4b4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -236,7 +236,38 @@ chip soc/intel/cannonlake end end # I2C #1 device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R |