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authorWisley Chen <wisley.chen@quanta.corp-partner.google.com>2018-10-09 17:04:59 +0800
committerFurquan Shaikh <furquan@google.com>2018-10-11 06:37:51 +0000
commita07efab72a6e4a44e8a3ad92a71b569e1f269426 (patch)
tree39ba2427d6d4a7ff0de3762037cde79ffb48914c /src/mainboard
parent806ad196f3f32ce227d63cc05ee522866df88c01 (diff)
downloadcoreboot-a07efab72a6e4a44e8a3ad92a71b569e1f269426.tar.xz
mb/google/octopus: I2C clock tuning for meep
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:117298114 TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/octopus/variants/meep/overridetree.cb41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb
index 42bd83bf63..691fa9e52b 100644
--- a/src/mainboard/google/octopus/variants/meep/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb
@@ -1,5 +1,46 @@
chip soc/intel/apollolake
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Digitizer |
+ #| I2C5 | Audio |
+ #| I2C6 | Trackpad |
+ #| I2C7 | Touchscreen |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 120,
+ .fall_time_ns = 30,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 104,
+ .fall_time_ns = 52,
+ },
+ .i2c[6] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
+ .data_hold_time_ns = 350,
+ },
+ .i2c[7] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 44,
+ .fall_time_ns = 90,
+ },
+ }"
+
device domain 0 on
device pci 16.0 on
chip drivers/i2c/hid