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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-25 11:40:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-11 08:57:41 +0100
commita6ac1877316216c8c56a9ab04b9ac3cde6ab01aa (patch)
tree68b39f9c23f7c6bd9ac19c2daa75f58ae057f1e8 /src/mainboard
parent823020d56be1bf6425b4e433a1f1c2bbc2c4c90b (diff)
downloadcoreboot-a6ac1877316216c8c56a9ab04b9ac3cde6ab01aa.tar.xz
intel/gm45: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17674 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/lenovo/t400/romstage.c17
-rw-r--r--src/mainboard/lenovo/x200/romstage.c17
-rw-r--r--src/mainboard/roda/rk9/romstage.c17
3 files changed, 12 insertions, 39 deletions
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 821b87f52a..d110d4fc44 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -156,18 +157,8 @@ void mainboard_romstage_entry(unsigned long bist)
outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
+
+ romstage_handoff_init(cbmem_initted && s3resume);
+
printk(BIOS_SPEW, "exit main()\n");
}
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 8c97ae1554..49c5528277 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -157,18 +158,8 @@ void mainboard_romstage_entry(unsigned long bist)
outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
+
+ romstage_handoff_init(cbmem_initted && s3resume);
+
printk(BIOS_SPEW, "exit main()\n");
}
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index e9a6a8182d..720f628ade 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -27,6 +27,7 @@
#include <cbmem.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
@@ -187,18 +188,8 @@ void mainboard_romstage_entry(unsigned long bist)
init_iommu();
cbmem_initted = !cbmem_recovery(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume && cbmem_initted) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC);
- } else {
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC);
- }
-#endif
+
+ romstage_handoff_init(cbmem_initted && s3resume);
+
printk(BIOS_SPEW, "exit main()\n");
}