diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-12-07 20:34:08 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-09 16:53:03 +0000 |
| commit | b3937bb10858a2767829b7eb3fc645a6b4ce9db2 (patch) | |
| tree | 6dbc332604a2ce72b9e2f69eb39f766e37c2a1ff /src/mainboard | |
| parent | 950252675ab4148621b6be092a4240f2d96ffba0 (diff) | |
| download | coreboot-b3937bb10858a2767829b7eb3fc645a6b4ce9db2.tar.xz | |
google/cyan: fix FSP memory init params
In the original Chromium source, PcdMemorySpdPtr is only set for
cyan, but none of the other Braswell variants. When upstreamed,
it was left set for all boards as it didn't appear to be problematic.
In wider testing, I came across one reks board for which it caused
FSP memory init to fail, so restricting the parameter to cyan only
as it was originally.
TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,
observe board now successfully boots where it did not previously.
Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22782
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/cyan/romstage.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index c164ea4792..5b4bcc0ebe 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -33,11 +33,13 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { /* Update SPD data */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { memory_params->PcdMemoryTypeEnable = MEM_DDR3; - else + memory_params->PcdMemorySpdPtr = + (u32)params->pei_data->spd_data_ch0; + } else memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; |