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authorChandana Kishori Chiluveru <cchiluve@codeaurora.org>2018-03-26 15:13:36 -0700
committerJulius Werner <jwerner@chromium.org>2019-05-02 23:06:06 +0000
commitc0fe0b28a9461e963d6dff5d91cf70231dcae0e8 (patch)
tree535ce069b581837415a945081ab34223db66797f /src/mainboard
parent7a3e46d767890f502b09771e19decc5033e27079 (diff)
downloadcoreboot-c0fe0b28a9461e963d6dff5d91cf70231dcae0e8.tar.xz
sdm845: Add USB support on cheza platform
This patch adds code to initialize two USB DWC3.0 controllers and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to initialize USB3.0 on the cheza mainboard. Synopsis controller initialization and configuration sequences taken from USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy programming. Includes Super speed mode support. TEST=USB keypad and mass-storage device enumeration tested with this patch Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/cheza/mainboard.c14
-rw-r--r--src/mainboard/google/cheza/romstage.c11
2 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
index cb4f5d061a..42adf56c79 100644
--- a/src/mainboard/google/cheza/mainboard.c
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -16,9 +16,23 @@
#include <device/device.h>
#include <bootblock_common.h>
#include <gpio.h>
+#include <timestamp.h>
+#include <soc/usb.h>
+
+static struct usb_board_data usb1_board_data = {
+ .pll_bias_control_2 = 0x28,
+ .imp_ctrl1 = 0x08,
+ .port_tune1 = 0x20,
+};
static void setup_usb(void)
{
+ /*
+ * Primary USB is used only for DP functionality on cheza platform.
+ * Hence Setting up only Secondary USB DWC3 controller.
+ */
+ setup_usb_host1(&usb1_board_data);
+
gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */
}
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c
index ad8506193d..7b7da4ce8c 100644
--- a/src/mainboard/google/cheza/romstage.c
+++ b/src/mainboard/google/cheza/romstage.c
@@ -14,7 +14,18 @@
*/
#include <arch/stages.h>
+#include <soc/usb.h>
+
+static void prepare_usb(void)
+{
+ /*
+ * Do DWC3 core and phy reset. Kick these resets
+ * off early so they get at least 1ms to settle.
+ */
+ reset_usb1();
+}
void platform_romstage_main(void)
{
+ prepare_usb();
}