summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-06-10 17:04:29 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-06-17 19:24:22 +0000
commitc9a345130532f5bef7bcd6daf12f6a1c8e9b898b (patch)
tree91cb3e3820875c6ec94c526c2be1847949475976 /src/mainboard
parent097e44901351f48972dbacd83e91ded4cb2efa33 (diff)
downloadcoreboot-c9a345130532f5bef7bcd6daf12f6a1c8e9b898b.tar.xz
mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000
Temporary workaround for S0ix issues related to FSP's handling of 0 value. When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this value which seems to be causing issues with s0ix. This is still being debugged and a final solution will be made when available BUG=b:159151238 TEST=flash image with workaround to volteer and verify that s0ix cycles correctly. Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 8ff790e6b9..8cd926cd88 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -150,12 +150,12 @@ chip soc/intel/tigerlake
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
- register "IomTypeCPortPadCfg[2]" = "0x0"
- register "IomTypeCPortPadCfg[3]" = "0x0"
- register "IomTypeCPortPadCfg[4]" = "0x0"
- register "IomTypeCPortPadCfg[5]" = "0x0"
- register "IomTypeCPortPadCfg[6]" = "0x0"
- register "IomTypeCPortPadCfg[7]" = "0x0"
+ register "IomTypeCPortPadCfg[2]" = "0x09000000"
+ register "IomTypeCPortPadCfg[3]" = "0x09000000"
+ register "IomTypeCPortPadCfg[4]" = "0x09000000"
+ register "IomTypeCPortPadCfg[5]" = "0x09000000"
+ register "IomTypeCPortPadCfg[6]" = "0x09000000"
+ register "IomTypeCPortPadCfg[7]" = "0x09000000"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"