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authorGreg Watson <jarrah@users.sourceforge.net>2004-06-04 22:27:33 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-06-04 22:27:33 +0000
commitcb5f0ce6a74e94b964ab2c37ab41a03a4c8b966d (patch)
tree767d422003f3a8a009fba7db786f00fd416062a6 /src/mainboard
parent91d60a8fcab3e25b35f679fd7260d538bc758f02 (diff)
downloadcoreboot-cb5f0ce6a74e94b964ab2c37ab41a03a4c8b966d.tar.xz
fix addressing
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/totalimpact/briq/Config.lb21
1 files changed, 16 insertions, 5 deletions
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 1a1c66c5a0..6c54d85120 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -2,19 +2,30 @@
## Config file for the Total Impact briQ
##
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
+uses TTYS0_DIV
uses TTYS0_BASE
uses CONFIG_BRIQ_750FX
uses CONFIG_BRIQ_7400
+uses ISA_IO_BASE
+uses ISA_MEM_BASE
+uses PCIC0_CFGADDR
+uses PCIC0_CFGDATA
+uses _IO_BASE
##
-## Set PCI registers
+## Set memory map
##
-default PCIC0_CFGADDR=0xff508000
-default PCIC0_CFGDATA=0xff508010
+default ISA_IO_BASE=0x80000000
+default ISA_MEM_BASE=0xc0000000
+default PCIC0_CFGADDR=0xff5f8000
+default PCIC0_CFGDATA=0xff5f8010
+default _IO_BASE=ISA_IO_BASE
##
+## The briQ uses weird clocking, 4 = 115200
+##
+default TTYS0_DIV=4
+##
## Set UART base address
##
default TTYS0_BASE=0x3f8