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authorJohn Zhao <john.zhao@intel.com>2020-07-28 11:36:07 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-07-29 22:46:57 +0000
commitefcfaa8b6c954fa3b97a9e7a459a1f1cf13c8bc9 (patch)
tree4fcf4bcd02fa0998b82ced7b86c8f26af48acf44 /src/mainboard
parent5fdf2760a5952df22e5b331bc4f62082d8cec1bc (diff)
downloadcoreboot-efcfaa8b6c954fa3b97a9e7a459a1f1cf13c8bc9.tar.xz
mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration
It is expected both of TCSS D3Hot and D3Cold are enabled by default. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb4
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index e8dc7bd8cb..85f9e51084 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -117,10 +117,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS
- register "TcssD3HotEnable" = "1"
- register "TcssD3ColdEnable" = "1"
-
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index ef8de3cb2d..5c275b3951 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -113,10 +113,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS
- register "TcssD3HotEnable" = "1"
- register "TcssD3ColdEnable" = "1"
-
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"