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| author | nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> | 2020-06-30 09:34:33 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-06 20:32:11 +0000 |
| commit | f446b81f8fc9247d393edb2447f0afbd2829a637 (patch) | |
| tree | 1642687166be62ae87ec9b1430bb8592c0840b03 /src/mainboard | |
| parent | d9dea6561585d0d69f2df277a81616137230a7ba (diff) | |
| download | coreboot-f446b81f8fc9247d393edb2447f0afbd2829a637.tar.xz | |
mb/google/volteer: Enable HotPlug on PCIe root port for the SD express
Enable HotPlug for the PCIe root port that the SD express is on so the
OS can re-train the link without needing a reboot if it goes down
unexpectedly at runtime.
BUG=b:156879564
BRANCH=master
TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in
linux that it is identified as a HotPlug capable root port
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 300fb7e729..88aff01c0a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -86,6 +86,7 @@ chip soc/intel/tigerlake # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + register "PcieRpHotPlug[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" |