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authorAaron Durbin <adurbin@chromium.org>2015-08-07 22:57:42 -0500
committerAaron Durbin <adurbin@chromium.org>2015-08-14 15:20:46 +0200
commitf50b25d7e2c979e2b8cddb76039afcdeb686e1c0 (patch)
treebff6948ef7335999a139fadf5b682f66ca4a4333 /src/mainboard
parent9a8dc37cdd9486926c6b5416dd48f4f075b2612d (diff)
downloadcoreboot-f50b25d7e2c979e2b8cddb76039afcdeb686e1c0.tar.xz
skylake: remove ec_smi_gpio and alt_gp_smi_en
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb5
-rw-r--r--src/mainboard/intel/sklrvp/devicetree.cb4
2 files changed, 2 insertions, 7 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 7f1b35f438..6f03bbf793 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -28,11 +28,8 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
- # EC_SMI
- register "ec_smi_gpio" = "34"
- register "alt_gp_smi_en" = "0x0400"
+ # GPE configuration
register "gpe0_en_1" = "0x00000000"
-
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_3" = "0x00000000"
diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb
index 128c22261b..cfa51a89d2 100644
--- a/src/mainboard/intel/sklrvp/devicetree.cb
+++ b/src/mainboard/intel/sklrvp/devicetree.cb
@@ -49,9 +49,7 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
- # EC_SMI
- register "ec_smi_gpio" = "34"
- register "alt_gp_smi_en" = "0x0400"
+ # GPE configuration
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"