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authorRyback Hung <ryback.hung%quantatw.com@gtempaccount.com>2020-04-16 19:34:03 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-05-01 16:40:11 +0000
commitf87ad9225c5dfafc266071bb4757065bca50966f (patch)
treec6690771411cc65c4923533ddf10a86fee0fd97f /src/mainboard
parentd2bbc68fa32ec60f8aa83870559beadbef0d1c9f (diff)
downloadcoreboot-f87ad9225c5dfafc266071bb4757065bca50966f.tar.xz
mb/ocp/sonorapass: Add Sonora Pass
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/ocp/sonorapass/Kconfig31
-rw-r--r--src/mainboard/ocp/sonorapass/Kconfig.name2
-rw-r--r--src/mainboard/ocp/sonorapass/Makefile.inc1
-rw-r--r--src/mainboard/ocp/sonorapass/acpi/platform.asl44
-rw-r--r--src/mainboard/ocp/sonorapass/board.fmd10
-rw-r--r--src/mainboard/ocp/sonorapass/board_info.txt5
-rw-r--r--src/mainboard/ocp/sonorapass/bootblock.c68
-rw-r--r--src/mainboard/ocp/sonorapass/devicetree.cb39
-rw-r--r--src/mainboard/ocp/sonorapass/dsdt.asl59
9 files changed, 259 insertions, 0 deletions
diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig
new file mode 100644
index 0000000000..7e8e20ee7c
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/Kconfig
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# This file is part of the coreboot project.
+
+if BOARD_OCP_SONORAPASS
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_65536
+ select MAINBOARD_USES_FSP2_0
+ select IPMI_KCS
+ select SOC_INTEL_COOPERLAKE_SP
+ select SUPERIO_ASPEED_AST2400
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default "ocp/sonorapass"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "SonoraPass"
+
+config MAINBOARD_FAMILY
+ string
+ default "SonoraPass"
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+endif
diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name
new file mode 100644
index 0000000000..90e7f3dfdf
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_OCP_SONORAPASS
+ bool "SonoraPass"
diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc
new file mode 100644
index 0000000000..8501868fbf
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/Makefile.inc
@@ -0,0 +1 @@
+bootblock-y += bootblock.c
diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl
new file mode 100644
index 0000000000..75c1b92f1e
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/acpi/platform.asl
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+Name(\APC1, Zero) // IIO IOAPIC
+
+Name(\PICM, Zero) // IOAPIC/8259
+
+Method(_PIC, 1)
+{
+ Store(Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd
new file mode 100644
index 0000000000..e28bcf08c0
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/board.fmd
@@ -0,0 +1,10 @@
+FLASH@0xfc000000 64M {
+ SI_ALL@0x0 0x2fd8000 {
+ SI_DESC@0x0 0x1000
+ SI_GBE@0x1000 0x2000
+ SI_ME@0x3000 0x2fc5000
+ }
+ FMAP@0x03000000 0x800
+ RW_MRC_CACHE@0x3000800 0x10000
+ COREBOOT(CBFS)@0x3010800
+}
diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt
new file mode 100644
index 0000000000..bbf3ee9b9d
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/board_info.txt
@@ -0,0 +1,5 @@
+Board name: SonoraPass
+Category: server
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c
new file mode 100644
index 0000000000..ba02208cab
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/bootblock.c
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pnp_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+
+#define ASPEED_CONFIG_INDEX 0x2E
+#define ASPEED_CONFIG_DATA 0x2F
+
+static void enable_espi_lpc_io_windows(void)
+{
+ /*
+ * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
+ * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+ * For that end it is wired into BMC virtual port.
+ */
+
+ /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */
+ pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4));
+ /* LPC I/O enable: com1 and com2 */
+ pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
+
+ /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+ pci_mmio_write_config32(PCH_DEV_LPC, 0x80,
+ (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4));
+}
+
+static uint8_t com_to_ast_sio(uint8_t com)
+{
+ switch (com) {
+ case 0:
+ return AST2400_SUART1;
+ case 1:
+ return AST2400_SUART2;
+ case 2:
+ return AST2400_SUART3;
+ case 4:
+ return AST2400_SUART4;
+ default:
+ return AST2400_SUART1;
+ }
+}
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Open IO windows */
+ enable_espi_lpc_io_windows();
+
+ /* Configure appropriate physical port of SuperIO chip off BMC */
+ const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX,
+ com_to_ast_sio(CONFIG_UART_FOR_CONSOLE));
+ aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+ /* Port 80h direct to GPIO for LED display */
+ const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO);
+ aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH);
+
+ /* Enable UART function pin*/
+ aspeed_enable_uart_pin(serial_dev);
+}
diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb
new file mode 100644
index 0000000000..05dac455e3
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/devicetree.cb
@@ -0,0 +1,39 @@
+chip soc/intel/xeon_sp/cpx
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host bridge
+ device pci 04.0 on end
+ device pci 04.1 on end
+ device pci 04.2 on end
+ device pci 04.3 on end
+ device pci 04.4 on end
+ device pci 04.5 on end
+ device pci 04.6 on end
+ device pci 04.7 on end
+ device pci 05.0 on end
+ device pci 05.2 on end
+ device pci 05.4 on end
+ device pci 08.0 on end
+ device pci 08.1 on end
+ device pci 08.2 on end
+ device pci 11.0 on end
+ device pci 11.1 on end
+ device pci 11.5 on end
+ device pci 14.0 on end
+ device pci 16.0 on end
+ device pci 16.1 on end
+ device pci 16.4 on end
+ device pci 17.0 on end
+ device pci 1c.0 on end
+ device pci 1c.4 on end
+ device pci 1f.2 on end
+ device pci 1f.4 on end
+ device pci 1f.5 on end
+
+ device pci 1f.0 on # LPC/eSPI Interface
+ end
+
+ end
+end
diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl
new file mode 100644
index 0000000000..3dc45d5f2c
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/dsdt.asl
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/acpi.h>
+#include <soc/iomap.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include "acpi/platform.asl"
+
+ Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
+ Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
+
+ Scope (\_SB)
+ {
+ Device (PCI0)
+ {
+ #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl>
+ #include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+ }
+
+
+ Device (UNC0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_UID, 0x3F)
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (0xff)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xf)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x00FF, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+
+ }
+ }
+
+}