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authorPatrick Rudolph <siro@das-labor.org>2016-02-06 18:07:59 +0100
committerMartin Roth <martinroth@google.com>2016-02-23 00:28:06 +0100
commit273a8dca1f7896c73b812ecc2c6cd2572ac51d6a (patch)
treea086a9e33bcef9c6490c6cc706a5aef79651f3b5 /src/mainboard
parent9a4881a783fa1edc730dc484bb2c293d92e45823 (diff)
downloadcoreboot-273a8dca1f7896c73b812ecc2c6cd2572ac51d6a.tar.xz
southbridge/intel/lynxpoint: Use common gpio.c
Use shared gpio code from common folder, except for INTEL_LYNXPOINT_LP, which has it's own gpio code. Needs test on real hardware ! Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/bolt/chromeos.c1
-rw-r--r--src/mainboard/google/falco/chromeos.c1
-rw-r--r--src/mainboard/google/falco/smihandler.c1
-rw-r--r--src/mainboard/google/panther/chromeos.c1
-rw-r--r--src/mainboard/google/peppy/chromeos.c1
-rw-r--r--src/mainboard/google/peppy/smihandler.c1
-rw-r--r--src/mainboard/google/slippy/chromeos.c1
-rw-r--r--src/mainboard/intel/baskingridge/chromeos.c24
-rw-r--r--src/mainboard/intel/baskingridge/gpio.h2
9 files changed, 11 insertions, 22 deletions
diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c
index 2f393e0172..ff0a1f748c 100644
--- a/src/mainboard/google/bolt/chromeos.c
+++ b/src/mainboard/google/bolt/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c
index a7d96a8562..f0e6a5aa85 100644
--- a/src/mainboard/google/falco/chromeos.c
+++ b/src/mainboard/google/falco/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c
index c1b3fcf001..6f17e40240 100644
--- a/src/mainboard/google/falco/smihandler.c
+++ b/src/mainboard/google/falco/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c
index 2c5c234ca2..17917b1a8e 100644
--- a/src/mainboard/google/panther/chromeos.c
+++ b/src/mainboard/google/panther/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 58
diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c
index a7d96a8562..f0e6a5aa85 100644
--- a/src/mainboard/google/peppy/chromeos.c
+++ b/src/mainboard/google/peppy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c
index 9e7657a301..8f265a03a8 100644
--- a/src/mainboard/google/peppy/smihandler.c
+++ b/src/mainboard/google/peppy/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
index a7d96a8562..f0e6a5aa85 100644
--- a/src/mainboard/google/slippy/chromeos.c
+++ b/src/mainboard/google/slippy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 3885257851..94e8d89a06 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/gpio.h>
+#include <southbridge/intel/common/gpio.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -82,38 +82,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
-
/*
* Developer: GPIO48, Connected to J8E4, however the silkscreen says
* J8E3. The jumper is active low.
*/
- return !((gp_lvl2 >> (48-32)) & 1);
+ return !get_gpio(48);
}
int get_recovery_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
/*
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
- return (gp_lvl3 >> (69-64)) & 1;
+ return get_gpio(69);
}
int get_write_protect_state(void)
diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h
index 99bec38886..f2be9e3c84 100644
--- a/src/mainboard/intel/baskingridge/gpio.h
+++ b/src/mainboard/intel/baskingridge/gpio.h
@@ -16,7 +16,7 @@
#ifndef BASKING_RIDGE_GPIO_H
#define BASKING_RIDGE_GPIO_H
-#include "southbridge/intel/lynxpoint/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F4 */