haswell: adjust CAR usage

It was found that the Haswell reference code was smashing through the
stack into the reference code's heap implementation. The reason for this
is because our current CAR allocation is too small. Moreover there are
quite a few things to coordinate between 2 code bases to get correct.
This commit separates the CAR into 2 parts:
  1. MRC CAR usage.
  2. Coreboot CAR usage.
Pointers from one region can be passed between the 2 modules, but one
should not be able to affect the others as checking has been put into
place in both modules.

The CAR size has effectively been doubled from 0x20000 (128 KiB) to
0x40000 (256KiB). Not all of that increase was needed, but enforcing
a power of 2 size only utilizes 1 MTRR.

Old CAR layout with a single contiguous stack with the region starting
at CONFIG_DCACHE_RAM_BASE:

+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
|  MRC global variables                 |
|  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+
|  ROM stage stack                      |
|                                       |
|                                       |
+---------------------------------------+
|  MRC Heap 30000 bytes                 |
+---------------------------------------+
|  ROM stage console                    |
|  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
|  ROM stage CAR_GLOBAL variables       |
+---------------------------------------+ Offset 0

There was some hard coded offsets in the reference code wrapper to start
the heap past the console buffer. Even with this commit the console
can smash into the following region depending on what size
CONFIG_CONSOLE_CAR_BUFFER_SIZE is.

As noted above This change splits the CAR region into 2 parts starting
at CONFIG_DCACHE_RAM_BASE:

+---------------------------------------+
|  MRC Region                           |
|  CONFIG_DCACHE_RAM_MRC_VAR_SIZE bytes |
+---------------------------------------+ Offset CONFIG_DCACHE_RAM_SIZE
|  ROM stage stack                      |
|                                       |
|                                       |
+---------------------------------------+
|  ROM stage console                    |
|  CONFIG_CONSOLE_CAR_BUFFER_SIZE bytes |
+---------------------------------------+
|  ROM stage CAR_GLOBAL variables       |
+---------------------------------------+ Offset 0

Another variable was add, CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE,
which represents the expected stack usage for the romstage. A marker
is checked at the base of the stack to determine if either the stack
was smashed or the console encroached on the stack.

Change-Id: Id76f2fe4a5cf1c776c8f0019f406593f68e443a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2752
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

3 files changed, 7 insertions, 15 deletions

diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index d47fbf13a2..45316f62b9 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -30,6 +30,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include "cpu/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/pch.h"
@@ -82,7 +83,7 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void main(unsigned long bist)
+void romstage_main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int wake_from_s3;
@@ -236,8 +237,5 @@ void main(unsigned long bist)
 	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
 	timestamp_add_now(TS_END_ROMSTAGE);
 #endif
-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
 }
+
diff --git a/src/mainboard/intel/wtm1/romstage.c b/src/mainboard/intel/wtm1/romstage.c
index 0190964b26..c80c721eaf 100644
--- a/src/mainboard/intel/wtm1/romstage.c
+++ b/src/mainboard/intel/wtm1/romstage.c
@@ -30,6 +30,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include "cpu/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/me.h"
@@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void main(unsigned long bist)
+void romstage_main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int wake_from_s3;
@@ -241,8 +242,4 @@ void main(unsigned long bist)
 	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
 	timestamp_add_now(TS_END_ROMSTAGE);
 #endif
-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
 }
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 100195b485..a4a42d3f70 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -30,6 +30,7 @@
 #include <pc80/mc146818rtc.h>
 #include <cbmem.h>
 #include <console/console.h>
+#include "cpu/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/raminit.h"
 #include "southbridge/intel/lynxpoint/me.h"
@@ -87,7 +88,7 @@ const struct rcba_config_instruction rcba_config[] = {
 	RCBA_END_CONFIG,
 };
 
-void main(unsigned long bist)
+void romstage_main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int wake_from_s3;
@@ -241,8 +242,4 @@ void main(unsigned long bist)
 	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
 	timestamp_add_now(TS_END_ROMSTAGE);
 #endif
-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
 }