gigabyte/ga-b75m-d3v: Add GIGABYTE GA-B75M-D3V mainboard

Board boots to linux. VGA works with rom. Change-Id: I96b73a90c3d88672f0d238f4b735cd2f96ef99bd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/9803 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
author: Damien Zammit <damien@zamaudio.com> 2015-04-20 16:53:36 +1000
committer: Edward O'Callaghan <edward.ocallaghan@koparo.com> 2015-04-20 23:55:36 +0200
commit: 4038a7f631dce05aa184184a225a49bc7723aed0 (patch)
tree: d0130aae12ce4b1906e9fb5ab1c9e83eb565c557 /src/mainboard
parent: 31ca97c38c29eb08558ac104631989544da4bfc8 (diff)
download: coreboot-4038a7f631dce05aa184184a225a49bc7723aed0.tar.xz
21 files changed, 1470 insertions, 0 deletions
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
new file mode 100644
index 0000000000..cffc7f00f4
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_GIGABYTE_GA_B75M_D3V
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA1155
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
+	select SOUTHBRIDGE_INTEL_C216
+	select CPU_MICROCODE_CBFS_NONE
+	select SUPERIO_ITE_IT8728F
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_ACPI_RESUME
+	select HAVE_SMI_HANDLER
+	select INTEL_INT15
+	select VGA
+	select INTEL_EDID
+	select UDELAY_TSC
+        select SERIRQ_CONTINUOUS_MODE
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf8000000
+
+config DRAM_RESET_GATE_GPIO
+        int
+	default 25
+
+config USBDEBUG_HCD_INDEX
+       int
+       default 2
+
+config MAINBOARD_DIR
+        string
+        default gigabyte/ga-b75m-d3v
+
+config MAINBOARD_PART_NUMBER
+        string
+        default "GA-B75M-D3V"
+
+config IRQ_SLOT_COUNT
+        int
+        default 18
+
+config MAX_CPUS
+        int
+        default 8
+
+config VGA_BIOS_ID
+	string
+	default "8086,0102"
+
+config VGA_BIOS_FILE
+        string
+        default "pci8086,0102.rom"
+
+config HAVE_IFD_BIN
+	bool
+	default n
+
+config HAVE_ME_BIN
+	bool
+	default n
+
+config IFD_BIOS_SECTION
+        string
+        default "0x00600000:0x007fffff"
+
+config IFD_ME_SECTION
+        string
+        default "0x00001000:0x004fffff"
+
+endif # BOARD_GIGABYTE_GA_B75M_D3V
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name
new file mode 100644
index 0000000000..92f5744f2d
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_B75M_D3V
+	bool "GA-B75M-D3V"
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc
new file mode 100644
index 0000000000..a2efaddcef
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+romstage-y += gpio.c
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/ec.asl
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
new file mode 100644
index 0000000000..0db01bb950
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Method (BRTN, 1, Serialized)
+{
+	If (LEqual (And (DID1, 0x0F00), 0x0400))
+	{
+		Notify (\_SB.PCI0.GFX0.DD01, Arg0)
+	}
+
+	If (LEqual (And (DID2, 0x0F00), 0x0400))
+	{
+		Notify (\_SB.PCI0.GFX0.DD02, Arg0)
+	}
+
+	If (LEqual (And (DID3, 0x0F00), 0x0400))
+	{
+		Notify (\_SB.PCI0.GFX0.DD03, Arg0)
+	}
+
+	If (LEqual (And (DID4, 0x0F00), 0x0400))
+	{
+		Notify (\_SB.PCI0.GFX0.DD04, Arg0)
+	}
+
+	If (LEqual (And (DID5, 0x0F00), 0x0400))
+	{
+		Notify (\_SB.PCI0.GFX0.DD05, Arg0)
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
new file mode 100644
index 0000000000..3f63b8e5ad
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
new file mode 100644
index 0000000000..4c50b6c689
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
@@ -0,0 +1,4 @@
+/* mainboard configuration */
+
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // Enable PS/2 Mouse
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl
new file mode 100644
index 0000000000..f71611afcd
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/thermal.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x03)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 10 seconds
+		Name (_TSP, 100)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1)
+		{
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
new file mode 100644
index 0000000000..f87af3c192
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/video.asl
@@ -0,0 +1 @@
+// Blank
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
new file mode 100644
index 0000000000..73b1c11f84
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+	// the lid is open by default.
+	gnvs->lids = 1;
+
+	acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
new file mode 100644
index 0000000000..65bdd22261
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL:
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
new file mode 100644
index 0000000000..21d75e5ece
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+last_boot=Fallback
+baud_rate=115200
+debug_level=Spew
+power_on_after_fail=Enable
+nmi=Enable
+volume=0x3
+sata_mode=AHCI
+hyper_threading=Enable
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
new file mode 100644
index 0000000000..ca70c712b6
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/cmos.layout
@@ -0,0 +1,130 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+400          8       h       0        volume
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+
+#411       10       r       0        unused
+421         1       e       9        sata_mode
+#422	    2	    r	    0	     unused
+
+# coreboot config options: cpu
+424          1       e       2        hyper_threading
+#425        7       r       0        unused
+
+# coreboot config options: northbridge
+432         3        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+9     0     AHCI
+9     1     IDE
+11    0     32M
+11    1     64M
+11    2	    96M
+11    3	    128M
+11    4	    160M
+11    5	    192M
+11    6	    224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
new file mode 100644
index 0000000000..1c08359cb3
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
@@ -0,0 +1,118 @@
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_LGA1155
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			register "pstate_coord_type" = "0xfe"
+			register "c1_acpower" = "1"
+			register "c2_acpower" = "3"
+			register "c3_acpower" = "5"
+			register "c1_battery" = "1"
+			register "c2_battery" = "3"
+			register "c3_battery" = "5"
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1458 0x5000 inherit
+		device pci 00.0 on # host bridge
+			subsystemid 0x1458 0x5000
+		end
+		device pci 01.0 on end # PCIe Bridge for discrete graphics
+		device pci 02.0 on # vga controller
+			subsystemid 0x1458 0xd000
+		end
+
+		chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
+
+			# GPI routing
+			register "alt_gp_smi_en" = "0x0000"
+			register "gen1_dec" = "0x003c0a01"
+
+			# Set max SATA speed to 6.0 Gb/s
+			register "sata_port_map" = "0x3f"
+			register "sata_interface_speed_support" = "0x3"
+
+			register "pcie_port_coalesce" = "0"
+			register "p_cnt_throttling_supported" = "0"
+			register "docking_supported" = "0"
+			register "c2_latency" = "0x0065"
+
+			device pci 14.0 on # USB 3.0 Controller
+				subsystemid 0x1458 0x5007
+			end
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x1458 0x5006
+			end
+			device pci 1b.0 on # High Definition Audio
+				subsystemid 0x1458 0xa002
+			end
+			device pci 1c.0 on end # PCIe Port #1
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 on # PCIe Port #5
+				device pci 00.0 on # PCI 10ec:8168
+					subsystemid 0x1458 0xe000
+				end
+			end
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x1458 0x5006
+			end
+			device pci 1e.0 on end # PCI bridge
+			device pci 1f.0 on # ISA/LPC bridge
+				subsystemid 0x1458 0x5001
+				chip superio/ite/it8728f
+					device pnp 2e.0 off end # FDC
+					device pnp 2e.1 on # Serial Port 1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.2 on
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.3 on
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 4
+					end
+					device pnp 2e.4 on # EC
+						io 0x60 = 0xa30
+						irq 0x70 = 9
+						io 0x62 = 0xa20
+					end
+					device pnp 2e.5 on # Keyboard
+						io 0x60 = 0x60
+						irq 0x70 = 1
+						io 0x62 = 0x64
+					end
+					device pnp 2e.6 on # Mouse
+						irq 0x70 = 12
+					end
+					device pnp 2e.7 off end # GPIO
+					device pnp 2e.a off end # IR
+				end
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x1458 0xb005
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x1458 0x5001
+			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end # SATA Controller 2
+		end
+	end
+end
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
new file mode 100644
index 0000000000..1ce6dd4236
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -0,0 +1,25 @@
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	/* global NVS and variables.  */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c
new file mode 100644
index 0000000000..1f2c5e7069
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/gpio.c
@@ -0,0 +1,433 @@
+#include "southbridge/intel/bd82x6x/gpio.h"
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_NATIVE,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_NATIVE,
+	.gpio7 = GPIO_MODE_NATIVE,
+	.gpio8 = GPIO_MODE_NATIVE,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_NATIVE,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_NATIVE,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_NATIVE,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_NATIVE,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_NATIVE,
+	.gpio28 = GPIO_MODE_NATIVE,
+	.gpio29 = GPIO_MODE_NATIVE,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_OUTPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	.gpio3 = GPIO_DIR_OUTPUT,
+	.gpio4 = GPIO_DIR_OUTPUT,
+	.gpio5 = GPIO_DIR_OUTPUT,
+	.gpio6 = GPIO_DIR_OUTPUT,
+	.gpio7 = GPIO_DIR_OUTPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio9 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_OUTPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_OUTPUT,
+	.gpio14 = GPIO_DIR_OUTPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio18 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_OUTPUT,
+	.gpio20 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_OUTPUT,
+	.gpio26 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_HIGH,
+	.gpio1 = GPIO_LEVEL_HIGH,
+	.gpio2 = GPIO_LEVEL_HIGH,
+	.gpio3 = GPIO_LEVEL_HIGH,
+	.gpio4 = GPIO_LEVEL_HIGH,
+	.gpio5 = GPIO_LEVEL_HIGH,
+	.gpio6 = GPIO_LEVEL_HIGH,
+	.gpio7 = GPIO_LEVEL_HIGH,
+	.gpio8 = GPIO_LEVEL_LOW,
+	.gpio9 = GPIO_LEVEL_HIGH,
+	.gpio10 = GPIO_LEVEL_HIGH,
+	.gpio11 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio13 = GPIO_LEVEL_HIGH,
+	.gpio14 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_HIGH,
+	.gpio17 = GPIO_LEVEL_LOW,
+	.gpio18 = GPIO_LEVEL_HIGH,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio20 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_LOW,
+	.gpio23 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_HIGH,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+	.gpio30 = GPIO_LEVEL_HIGH,
+	.gpio31 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio0 = GPIO_RESET_PWROK,
+	.gpio1 = GPIO_RESET_PWROK,
+	.gpio2 = GPIO_RESET_PWROK,
+	.gpio3 = GPIO_RESET_PWROK,
+	.gpio4 = GPIO_RESET_PWROK,
+	.gpio5 = GPIO_RESET_PWROK,
+	.gpio6 = GPIO_RESET_PWROK,
+	.gpio7 = GPIO_RESET_PWROK,
+	.gpio8 = GPIO_RESET_PWROK,
+	.gpio9 = GPIO_RESET_PWROK,
+	.gpio10 = GPIO_RESET_PWROK,
+	.gpio11 = GPIO_RESET_PWROK,
+	.gpio12 = GPIO_RESET_PWROK,
+	.gpio13 = GPIO_RESET_PWROK,
+	.gpio14 = GPIO_RESET_PWROK,
+	.gpio15 = GPIO_RESET_PWROK,
+	.gpio16 = GPIO_RESET_PWROK,
+	.gpio17 = GPIO_RESET_PWROK,
+	.gpio18 = GPIO_RESET_PWROK,
+	.gpio19 = GPIO_RESET_PWROK,
+	.gpio20 = GPIO_RESET_PWROK,
+	.gpio21 = GPIO_RESET_PWROK,
+	.gpio22 = GPIO_RESET_PWROK,
+	.gpio23 = GPIO_RESET_PWROK,
+	.gpio24 = GPIO_RESET_RSMRST,
+	.gpio25 = GPIO_RESET_PWROK,
+	.gpio26 = GPIO_RESET_PWROK,
+	.gpio27 = GPIO_RESET_PWROK,
+	.gpio28 = GPIO_RESET_PWROK,
+	.gpio29 = GPIO_RESET_PWROK,
+	.gpio30 = GPIO_RESET_PWROK,
+	.gpio31 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_NO_INVERT,
+	.gpio1 = GPIO_NO_INVERT,
+	.gpio2 = GPIO_NO_INVERT,
+	.gpio3 = GPIO_NO_INVERT,
+	.gpio4 = GPIO_NO_INVERT,
+	.gpio5 = GPIO_NO_INVERT,
+	.gpio6 = GPIO_NO_INVERT,
+	.gpio7 = GPIO_NO_INVERT,
+	.gpio8 = GPIO_NO_INVERT,
+	.gpio9 = GPIO_NO_INVERT,
+	.gpio10 = GPIO_NO_INVERT,
+	.gpio11 = GPIO_NO_INVERT,
+	.gpio12 = GPIO_NO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_NO_INVERT,
+	.gpio15 = GPIO_NO_INVERT,
+	.gpio16 = GPIO_NO_INVERT,
+	.gpio17 = GPIO_NO_INVERT,
+	.gpio18 = GPIO_NO_INVERT,
+	.gpio19 = GPIO_NO_INVERT,
+	.gpio20 = GPIO_NO_INVERT,
+	.gpio21 = GPIO_NO_INVERT,
+	.gpio22 = GPIO_NO_INVERT,
+	.gpio23 = GPIO_NO_INVERT,
+	.gpio24 = GPIO_NO_INVERT,
+	.gpio25 = GPIO_NO_INVERT,
+	.gpio26 = GPIO_NO_INVERT,
+	.gpio27 = GPIO_NO_INVERT,
+	.gpio28 = GPIO_NO_INVERT,
+	.gpio29 = GPIO_NO_INVERT,
+	.gpio30 = GPIO_NO_INVERT,
+	.gpio31 = GPIO_NO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+	.gpio0 = GPIO_NO_BLINK,
+	.gpio1 = GPIO_NO_BLINK,
+	.gpio2 = GPIO_NO_BLINK,
+	.gpio3 = GPIO_NO_BLINK,
+	.gpio4 = GPIO_NO_BLINK,
+	.gpio5 = GPIO_NO_BLINK,
+	.gpio6 = GPIO_NO_BLINK,
+	.gpio7 = GPIO_NO_BLINK,
+	.gpio8 = GPIO_NO_BLINK,
+	.gpio9 = GPIO_NO_BLINK,
+	.gpio10 = GPIO_NO_BLINK,
+	.gpio11 = GPIO_NO_BLINK,
+	.gpio12 = GPIO_NO_BLINK,
+	.gpio13 = GPIO_NO_BLINK,
+	.gpio14 = GPIO_NO_BLINK,
+	.gpio15 = GPIO_NO_BLINK,
+	.gpio16 = GPIO_NO_BLINK,
+	.gpio17 = GPIO_NO_BLINK,
+	.gpio18 = GPIO_BLINK,
+	.gpio19 = GPIO_NO_BLINK,
+	.gpio20 = GPIO_NO_BLINK,
+	.gpio21 = GPIO_NO_BLINK,
+	.gpio22 = GPIO_NO_BLINK,
+	.gpio23 = GPIO_NO_BLINK,
+	.gpio24 = GPIO_NO_BLINK,
+	.gpio25 = GPIO_NO_BLINK,
+	.gpio26 = GPIO_NO_BLINK,
+	.gpio27 = GPIO_NO_BLINK,
+	.gpio28 = GPIO_NO_BLINK,
+	.gpio29 = GPIO_NO_BLINK,
+	.gpio30 = GPIO_NO_BLINK,
+	.gpio31 = GPIO_NO_BLINK,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio47 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+	.gpio62 = GPIO_DIR_OUTPUT,
+	.gpio63 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_HIGH,
+	.gpio39 = GPIO_LEVEL_HIGH,
+	.gpio40 = GPIO_LEVEL_HIGH,
+	.gpio41 = GPIO_LEVEL_HIGH,
+	.gpio42 = GPIO_LEVEL_HIGH,
+	.gpio43 = GPIO_LEVEL_HIGH,
+	.gpio44 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_HIGH,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio47 = GPIO_LEVEL_LOW,
+	.gpio48 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio52 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_LOW,
+	.gpio54 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio56 = GPIO_LEVEL_LOW,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio58 = GPIO_LEVEL_HIGH,
+	.gpio59 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+	.gpio62 = GPIO_LEVEL_HIGH,
+	.gpio63 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio32 = GPIO_RESET_PWROK,
+	.gpio33 = GPIO_RESET_PWROK,
+	.gpio34 = GPIO_RESET_PWROK,
+	.gpio35 = GPIO_RESET_PWROK,
+	.gpio36 = GPIO_RESET_PWROK,
+	.gpio37 = GPIO_RESET_PWROK,
+	.gpio38 = GPIO_RESET_PWROK,
+	.gpio39 = GPIO_RESET_PWROK,
+	.gpio40 = GPIO_RESET_PWROK,
+	.gpio41 = GPIO_RESET_PWROK,
+	.gpio42 = GPIO_RESET_PWROK,
+	.gpio43 = GPIO_RESET_PWROK,
+	.gpio44 = GPIO_RESET_PWROK,
+	.gpio45 = GPIO_RESET_PWROK,
+	.gpio46 = GPIO_RESET_PWROK,
+	.gpio47 = GPIO_RESET_PWROK,
+	.gpio48 = GPIO_RESET_PWROK,
+	.gpio49 = GPIO_RESET_PWROK,
+	.gpio50 = GPIO_RESET_PWROK,
+	.gpio51 = GPIO_RESET_PWROK,
+	.gpio52 = GPIO_RESET_PWROK,
+	.gpio53 = GPIO_RESET_PWROK,
+	.gpio54 = GPIO_RESET_PWROK,
+	.gpio55 = GPIO_RESET_PWROK,
+	.gpio56 = GPIO_RESET_PWROK,
+	.gpio57 = GPIO_RESET_PWROK,
+	.gpio58 = GPIO_RESET_PWROK,
+	.gpio59 = GPIO_RESET_PWROK,
+	.gpio60 = GPIO_RESET_PWROK,
+	.gpio61 = GPIO_RESET_PWROK,
+	.gpio62 = GPIO_RESET_PWROK,
+	.gpio63 = GPIO_RESET_PWROK,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_OUTPUT,
+	.gpio65 = GPIO_DIR_OUTPUT,
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio67 = GPIO_DIR_OUTPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_HIGH,
+	.gpio65 = GPIO_LEVEL_HIGH,
+	.gpio66 = GPIO_LEVEL_HIGH,
+	.gpio67 = GPIO_LEVEL_HIGH,
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_LOW,
+	.gpio71 = GPIO_LEVEL_LOW,
+	.gpio72 = GPIO_LEVEL_HIGH,
+	.gpio73 = GPIO_LEVEL_LOW,
+	.gpio74 = GPIO_LEVEL_HIGH,
+	.gpio75 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+	.gpio64 = GPIO_RESET_PWROK,
+	.gpio65 = GPIO_RESET_PWROK,
+	.gpio66 = GPIO_RESET_PWROK,
+	.gpio67 = GPIO_RESET_PWROK,
+	.gpio68 = GPIO_RESET_PWROK,
+	.gpio69 = GPIO_RESET_PWROK,
+	.gpio70 = GPIO_RESET_PWROK,
+	.gpio71 = GPIO_RESET_PWROK,
+	.gpio72 = GPIO_RESET_PWROK,
+	.gpio73 = GPIO_RESET_PWROK,
+	.gpio74 = GPIO_RESET_PWROK,
+	.gpio75 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
new file mode 100644
index 0000000000..62688c91a9
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/hda_verb.c
@@ -0,0 +1,28 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0887,	// Realtek 887
+	0x1458a002,	// Subsystem ID
+	0x0000000e,	// Number of entries
+
+	/* Pin Widget Verb Table */
+	AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19c50),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181345f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0)
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
new file mode 100644
index 0000000000..0124baa179
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 Google Inc.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <drivers/intel/gma/int15.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <cbfs.h>
+#include <build.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+}
+
+const char *smbios_mainboard_bios_version(void)
+{
+	/* Satisfy thinkpad_acpi.  */
+	if (strlen(CONFIG_LOCALVERSION))
+		return "CBET4000 " CONFIG_LOCALVERSION;
+	else
+		return "CBET4000 " COREBOOT_VERSION;
+}
+
+
+
+static void mainboard_init(device_t dev)
+{
+	RCBA32(0x38c8) = 0x00002005;
+	RCBA32(0x38c4) = 0x00802005;
+	RCBA32(0x38c0) = 0x00000007;
+        RCBA32(0x2240) = 0x00330e71;
+        RCBA32(0x2244) = 0x003f0eb1;
+        RCBA32(0x2248) = 0x002102cd;
+        RCBA32(0x224c) = 0x00f60000;
+        RCBA32(0x2250) = 0x00020000;
+        RCBA32(0x2254) = 0x00e3004c;
+        RCBA32(0x2258) = 0x00e20bef;
+        RCBA32(0x2260) = 0x003304ed;
+        RCBA32(0x2278) = 0x001107c1;
+        RCBA32(0x227c) = 0x001d07e9;
+        RCBA32(0x2280) = 0x00e20000;
+        RCBA32(0x2284) = 0x00ee0000;
+        RCBA32(0x2288) = 0x005b05d3;
+        RCBA32(0x2318) = 0x04b8ff2e;
+        RCBA32(0x231c) = 0x03930f2e;
+        RCBA32(0x3808) = 0x005044a3;
+        RCBA32(0x3810) = 0x52410000;
+        RCBA32(0x3814) = 0x0000008a;
+        RCBA32(0x3818) = 0x00000006;
+        RCBA32(0x381c) = 0x0000072e;
+        RCBA32(0x3820) = 0x0000000a;
+        RCBA32(0x3824) = 0x00000123;
+        RCBA32(0x3828) = 0x00000009;
+        RCBA32(0x382c) = 0x00000001;
+        RCBA32(0x3834) = 0x0000061a;
+        RCBA32(0x3838) = 0x00000003;
+        RCBA32(0x383c) = 0x00000a76;
+        RCBA32(0x3840) = 0x00000004;
+        RCBA32(0x3844) = 0x0000e5e4;
+        RCBA32(0x3848) = 0x0000000e;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c
new file mode 100644
index 0000000000..35702f0879
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard_smi.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <pc80/mc146818rtc.h>
+#include <delay.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+	printk(BIOS_DEBUG, "initializing SMI\n");
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+	static int smm_initialized;
+
+	if (!smm_initialized) {
+		mainboard_smm_init();
+		smm_initialized = 1;
+	}
+
+	/* On success, the IO Trap Handler returns 1
+	 * On failure, the IO Trap Handler returns a value != 1 */
+	return 1;
+}
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 data)
+{
+	u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+	printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
+	       data);
+
+	if (!pmbase)
+		return 0;
+
+	switch (data) {
+	case APM_CNT_ACPI_ENABLE:
+		break;
+	case APM_CNT_ACPI_DISABLE:
+		break;
+	case APM_CNT_FINALIZE:
+		printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+			return 0;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+
+	default:
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
new file mode 100644
index 0000000000..3e2be90488
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define SUPERIO_BASE 0x2e
+#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
+#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
+#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <superio/ite/it8728f/it8728f.h>
+#include <superio/ite/common/ite.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static void it8728f_b75md3v_disable_reboot(device_t dev)
+{
+	/* GPIO SIO settings */
+	ite_reg_write(dev, 0xEF, 0x7E); // magic
+
+	ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
+	ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
+	ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
+	ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
+	ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
+	ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
+	ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
+	ite_reg_write(dev, 0xe9, 0x27); // bus select disable
+	ite_reg_write(dev, 0xf0, 0x10); // ?
+	ite_reg_write(dev, 0xf1, 0x42); // ?
+	ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+
+	/* EC SIO settings */
+	ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
+	ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
+	ite_reg_write(IT8728F_EC, 0xf9, 0x48);
+	ite_reg_write(IT8728F_EC, 0x60, 0x0a);
+	ite_reg_write(IT8728F_EC, 0x61, 0x30);
+	ite_reg_write(IT8728F_EC, 0x62, 0x0a);
+	ite_reg_write(IT8728F_EC, 0x63, 0x20);
+	ite_reg_write(IT8728F_EC, 0x30, 0x01);
+}
+
+void rcba_config(void)
+{
+	/* Disable unused devices (board specific) */
+	RCBA32(FD) = 0x17ee1fe1;
+
+	/* Enable HECI */
+	RCBA32(FD2) &= ~0x2;
+}
+
+void pch_enable_lpc(void)
+{
+	/*
+	 * Enable:
+	 *  EC Decode Range PortA30/A20
+	 *  SuperIO Port2E/2F
+	 *  PS/2 Keyboard/Mouse Port60/64
+	 *  FDD Port3F0h-3F5h and Port3F7h
+	 */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+			CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+        pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
+        pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+
+        pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
+
+	/* Initialize SuperIO */
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	it8728f_b75md3v_disable_reboot(SUPERIO_GPIO);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+        { 1, 5, 0 },
+        { 1, 5, 0 },
+        { 1, 5, 1 },
+        { 1, 5, 1 },
+        { 1, 5, 2 },
+        { 1, 5, 2 },
+        { 1, 5, 3 },
+        { 1, 5, 3 },
+        { 1, 5, 4 },
+        { 1, 5, 4 },
+        { 1, 5, 6 },
+        { 1, 5, 5 },
+        { 1, 5, 5 },
+        { 1, 5, 6 },
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+        read_spd (&spd[0], 0x50);
+        read_spd (&spd[1], 0x51);
+        read_spd (&spd[2], 0x52);
+        read_spd (&spd[3], 0x53);
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h
new file mode 100644
index 0000000000..ed08c8a2d1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/thermal.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef GAB75MD3H_THERMAL_H
+#define GAB75MD3H_THERMAL_H
+
+	/* Temperature which OS will shutdown at */
+	#define CRITICAL_TEMPERATURE	100
+
+	/* Temperature which OS will throttle CPU */
+	#define PASSIVE_TEMPERATURE	90
+
+#endif
author	Damien Zammit <damien@zamaudio.com>	2015-04-20 16:53:36 +1000
committer	Edward O'Callaghan <edward.ocallaghan@koparo.com>	2015-04-20 23:55:36 +0200
commit	4038a7f631dce05aa184184a225a49bc7723aed0 (patch)
tree	d0130aae12ce4b1906e9fb5ab1c9e83eb565c557 /src/mainboard
parent	31ca97c38c29eb08558ac104631989544da4bfc8 (diff)
download	coreboot-4038a7f631dce05aa184184a225a49bc7723aed0.tar.xz