diff options
| author | BryantOu <Bryant.Ou.Q@gmail.com> | 2020-04-17 01:41:35 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-30 17:45:50 +0000 |
| commit | 4e06c6eeb1179cf553c99eff6f2ae9888376fd67 (patch) | |
| tree | ebce139936ccc98665dc2953f0ba2092709f3fa0 /src/mainboard | |
| parent | b8bfe142c6bbaf3674e9d0ff70b42ca32bcb4df4 (diff) | |
| download | coreboot-4e06c6eeb1179cf553c99eff6f2ae9888376fd67.tar.xz | |
mb/ocp/tiogapass: Implement port 80h direct to GPIO and init UART pins
Enable aspeed's function that port 80h direct to GPIO for LED display,
refer to section 9.4 Port 80h Direct to GPIO Guide of aspeed's
Application Design Guide, also configure GPIO to UART for output
serial console messages.
Tested=Check if port 80h LED debug card can display POST codes at
early stage, and serial console can see the related messages.
Change-Id: I087d5a81b881533b4550c193e4e9720a134fb8e7
Signed-off-by: BryantOu <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40481
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/ocp/tiogapass/bootblock.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c index d507422d30..67808ef72a 100644 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -4,6 +4,7 @@ #include <bootblock_common.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/pnp_ops.h> #include <intelblocks/pcr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> @@ -13,6 +14,8 @@ /* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 +#define ASPEED_CONFIG_INDEX 0x2E +#define ASPEED_CONFIG_DATA 0x2F static void enable_espi_lpc_io_windows(void) { @@ -54,6 +57,14 @@ void bootblock_mainboard_early_init(void) enable_espi_lpc_io_windows(); /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + /* Port 80h direct to GPIO for LED display */ + const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); + aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); + + /* Enable UART function pin */ + aspeed_enable_uart_pin(serial_dev); } |