* clean up all but two warnings on artecgroup dbe61

* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
  on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
  to life)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

10 files changed, 56 insertions, 286 deletions

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 210e4e8c10..eeee9ec94e 100644
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -57,46 +57,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
-            u32 msrnum;
-            msr_t msr;
-      };
-
-static const struct msrinit msr_table[] = 
-{
-       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
-                                                                  * Rom Properties: Write Serialize, WriteProtect.
-                                                                  * RomBase: 0xFFFC0
-                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
-                                                                  * SysTop: 0x000A0 
-                                                                  * System Memory Properties:  (Write Back) */
-       {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
-       {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
-       {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-       
-       /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
-       {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-       {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
-  int i;
-       for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-                           wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup. */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -117,6 +85,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index d742f50026..e19b8ac257 100644
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -52,46 +52,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-
-	/* Setup access to the cache for under 1MB. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x0;		/* write back */
-	msr.lo = 0x0;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-
-	/* Setup access to the cache for under 640K. Note MC not setup yet. */
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU0 + 0x21, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup. */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -116,6 +84,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
index 62470f479c..6803b93756 100644
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ b/src/mainboard/artecgroup/dbe61/Kconfig
@@ -31,7 +31,7 @@ config IRQ_SLOT_COUNT
 	default 3
 	depends on BOARD_ARTECGROUP_DBE61
 
-config RAMBASE
-	hex
-	default 0x4000
-	depends on BOARD_ARTECGROUP_DBE61
+#config RAMBASE
+#	hex
+#	default 0x4000
+##	depends on BOARD_ARTECGROUP_DBE61
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 29120136a6..07fd548722 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -45,9 +45,9 @@ static int spd_read_byte(unsigned device, unsigned address)
 {
 	int i;
 
-	if (device == DIMM0){
-		for (i=0; i < (ARRAY_SIZE(spd_table)); i++){
-			if (spd_table[i].address == address){
+	if (device == DIMM0) {
+		for (i=0; i < (ARRAY_SIZE(spd_table)); i++) {
+			if (spd_table[i].address == address) {
 				return spd_table[i].data;
 			}
 		}
@@ -69,46 +69,14 @@ static int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
-	u32 msrnum;
-	msr_t msr;
-};
-
-static const struct msrinit msr_table[] = 
-{
-       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
-                                                                  * Rom Properties: Write Serialize, WriteProtect.
-                                                                  * RomBase: 0xFFFC0
-                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
-                                                                  * SysTop: 0x000A0 
-                                                                  * System Memory Properties:  (Write Back) */
-       {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
-       {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
-       {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-       
-       /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
-       {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-       {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-		wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -137,6 +105,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
@@ -144,8 +115,7 @@ void cache_as_ram_main(void)
 	sdram_initialize(1, memctrl);
 
 	/* Dump memory configuratation */
-	/*{
-	msr_t msr;
+#if 0
 	msr = rdmsr(MC_CF07_DATA);
 	print_debug("MC_CF07_DATA: ");
 	print_debug_hex32(MC_CF07_DATA);
@@ -173,9 +143,10 @@ void cache_as_ram_main(void)
 	print_debug_hex32(msr.lo);
 	msr = rdmsr(MC_CF8F_DATA);
 	print_debug(" \n");
-	}*/
+#endif
 
 	/* Check memory. */
-	/* ram_check(0x00000000, 640 * 1024); */
+	// ram_check(0x00000000, 640 * 1024);
+	// ram_check(1024 * 1024, 2 * 1024 * 1024);
 }
 
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index be696d97d4..4598e89ad9 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -35,30 +35,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-	/* Setup access to the MC for under 1MB. Note MC not setup yet. */
-	msr.hi = 0x24fffc02;
-	msr.lo =  0x10010000;
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff00;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo =  0xfff00;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -81,6 +65,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index f5fa9e9b0a..32ffda24d8 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -60,46 +60,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-
-	/* Setup access to the cache for under 1MB. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x0;		/* Write back */
-	msr.lo = 0x0;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-
-	/* Setup access to the cache for under 640K. Note MC not setup yet. */
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU0 + 0x21, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup. */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -120,6 +88,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index efaf1dd6be..8aedd6380e 100644
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -60,39 +60,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-
-	/* Setup access to the cache for under 1MB. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x0;		/* Write back */
-	msr.lo = 0x0;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-
-	/* Setup access to the cache for under 640K. Note MC not setup yet. */
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU0 + 0x21, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static const u16 sio_init_table[] = {	// hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
@@ -128,7 +96,7 @@ static void mb_gpio_init(void)
 	it8712f_exit_conf();
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -150,6 +118,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 51b1cf6d1d..5354c2b5d7 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -122,39 +122,7 @@ static int smc_send_config(unsigned char config_data)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-
-	/* Setup access to the cache for under 1MB. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x1000A000;	/* 0-A0000 write back */
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x0;		/* Write back */
-	msr.lo = 0x0;
-	wrmsr(CPU_RCONF_A0_BF, msr);
-	wrmsr(CPU_RCONF_C0_DF, msr);
-	wrmsr(CPU_RCONF_E0_FF, msr);
-
-	/* Setup access to the cache for under 640K. Note MC not setup yet. */
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU0 + 0x21, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff80;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0x80fffe0;
-	wrmsr(MSR_GLIU1 + 0x21, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static const u16 sio_init_table[] = { // hi=data, lo=index
 	0x0707,		// select LDN 7 (GPIO, SPI, watchdog, ...)
@@ -189,7 +157,7 @@ static void mb_gpio_init(void)
 	it8712f_exit_conf();
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	int err;
 	post_code(0x01);
@@ -212,6 +180,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index c4a9cc98e5..a9b6db5a6c 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -115,31 +115,14 @@ static u8 spd_read_byte(u8 device, u8 address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-static void msr_init(void)
-{
-	msr_t msr;
-
-	/* Setup access to the MC for under 1MB. Note MC not setup yet. */
-	msr.hi = 0x24fffc02;
-	msr.lo = 0x10010000;
-	wrmsr(CPU_RCONF_DEFAULT, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff00;
-	wrmsr(MSR_GLIU0 + 0x20, msr);
-
-	msr.hi = 0x20000000;
-	msr.lo = 0xfff00;
-	wrmsr(MSR_GLIU1 + 0x20, msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 /** Early mainboard specific GPIO setup. */
 static void mb_gpio_init(void)
 {
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
 		{.channel0 = {0x50}},
@@ -161,6 +144,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 60f2d21093..aa63ab4062 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -57,46 +57,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "lib/generic_sdram.c"
 #include "cpu/amd/model_lx/cpureginit.c"
 #include "cpu/amd/model_lx/syspreinit.c"
-
-struct msrinit {
-            u32 msrnum;
-            msr_t msr;
-      };
-
-static const struct msrinit msr_table[] = 
-{
-       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
-                                                                  * Rom Properties: Write Serialize, WriteProtect.
-                                                                  * RomBase: 0xFFFC0
-                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
-                                                                  * SysTop: 0x000A0 
-                                                                  * System Memory Properties:  (Write Back) */
-       {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
-       {CPU_RCONF_C0_DF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
-       {CPU_RCONF_E0_FF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
-       
-       /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
-       {MSR_GLIU0_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU0_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU0_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-       {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
-       {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
-       {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
-};
-
-static void msr_init(void)
-{
-  int i;
-       for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-                           wrmsr(msr_table[i].msrnum, msr_table[i].msr);
-}
+#include "cpu/amd/model_lx/msrinit.c"
 
 static void mb_gpio_init(void)
 {
 	/* Early mainboard specific GPIO setup. */
 }
 
-void cache_as_ram_main(void)
+void main(unsigned long bist)
 {
 	post_code(0x01);
 
@@ -118,6 +86,9 @@ void cache_as_ram_main(void)
 	uart_init();
 	console_init();
 
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 	pll_reset(ManualConf);
 
 	cpuRegInit();