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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-11 19:02:10 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-11 19:02:10 +0000 |
| commit | accb50a4e3db15629dd3bc24e602e3af47a974db (patch) | |
| tree | 0de54aa567ddf88b736c33684bf2636a1d94cf59 /src/mainboard | |
| parent | 735c5acdce4403de90258362705ece059b0cdffe (diff) | |
| download | coreboot-accb50a4e3db15629dd3bc24e602e3af47a974db.tar.xz | |
The ADL855PC was never confirmed working (in fact it's pretty sure that code
does not work as it is, but it's the only compile test case for i855pm). It's
the only board left using an ICH4 that does not use CAR. Change that.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/digitallogic/adl855pc/Kconfig | 14 | ||||
| -rw-r--r-- | src/mainboard/digitallogic/adl855pc/romstage.c | 38 |
2 files changed, 20 insertions, 32 deletions
diff --git a/src/mainboard/digitallogic/adl855pc/Kconfig b/src/mainboard/digitallogic/adl855pc/Kconfig index c44cbe41a5..78da8f1b1b 100644 --- a/src/mainboard/digitallogic/adl855pc/Kconfig +++ b/src/mainboard/digitallogic/adl855pc/Kconfig @@ -5,10 +5,12 @@ config BOARD_DIGITALLOGIC_ADL855PC select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -20,6 +22,16 @@ config MAINBOARD_PART_NUMBER default "smartModule855" depends on BOARD_DIGITALLOGIC_ADL855PC +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + config IRQ_SLOT_COUNT int default 5 diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 59e21388e8..2e1a96c91b 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -57,7 +57,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/reset_test.c" #include "lib/generic_sdram.c" -static void main(unsigned long bist) + +#include "cpu/intel/model_6bx/cache_as_ram_disable.c" + +void real_main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -67,7 +70,6 @@ static void main(unsigned long bist) }; if (bist == 0) { - early_mtrr_init(); #if 0 enable_lapic(); init_timer(); @@ -80,7 +82,6 @@ static void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if 0 print_pci_devices(); @@ -89,50 +90,25 @@ static void main(unsigned long bist) if(!bios_reset_detected()) { enable_smbus(); #if 0 - dump_spd_registers(&memctrl[0]); - // dump_smbus_registers(); + dump_spd_registers(&memctrl[0]); + dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } -#if 0 - else { - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - } -#endif #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0, 0)); -#endif -/* -#if 0 + // Check all of memory ram_check(0x00000000, msr.lo+(msr.hi<<32)); -#else -#if 0 // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); -#else // Check 16MB of memory @ 2GB ram_check(0x80000000, 0x81000000); #endif -#endif -*/ } |