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| author | Ronald G. Minnich <rminnich@gmail.com> | 2009-10-08 17:10:20 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2009-10-08 17:10:20 +0000 |
| commit | ea1522b016d3740f5b57e682de9d936cacac2406 (patch) | |
| tree | 22181df8dea43d9d1b42907ad9be179eab68db13 /src/mainboard | |
| parent | cc2b9f2abeaac660bb474fe4cc4e75eb70a8371b (diff) | |
| download | coreboot-ea1522b016d3740f5b57e682de9d936cacac2406.tar.xz | |
This dialogue on email was useful and hence included.
failover.inc MUST come after enable_sse or your CPU will hang.
> Can you say why?
yes. if you compile failover.c with romcc options that include sse,
then you'll see code like this in failover.inc:
mov eax, %xmm0
This will hang if you have not first enabled sse.
Verified yesterday on the dell s1850.
>
> Does it hang in the SSE code or in the failover code?
It will hang in failover code, if that code was compiled with sse enabled
AND if the sse registers are used.
>
> Does this mean that failover requires SSE in order to work?
It may or it may not.
But if you compile it with romcc options that include sse,
and it uses sse without sse being enabled, it will hang.
This is a particularly nasty bug in that the failover code is not
guaranteed to compile in a way that sse is used, even if sse is
enabled; hence, this could be very hard to catch.
I'm lucky this bug appeared as soon as it did.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/Makefile.romccboard.inc | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/mainboard/Makefile.romccboard.inc b/src/mainboard/Makefile.romccboard.inc index 054a4f93df..71ad740589 100644 --- a/src/mainboard/Makefile.romccboard.inc +++ b/src/mainboard/Makefile.romccboard.inc @@ -24,18 +24,16 @@ crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc crt0-y += ../../../../src/arch/i386/lib/cpu_reset.inc crt0-y += ../../../../src/arch/i386/lib/id.inc -crt0-y += failover.inc crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc -ifeq ($(CONFIG_CPU_AMD_GX1),y) -crt0-y += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc -crt0-y += ../../../../src/cpu/amd/model_gx1/gx_setup.inc -crt0-y += auto.inc -else -crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-$(CONFIG_CPU_AMD_GX1) += ../../../../src/cpu/amd/model_gx1/cpu_setup.inc +crt0-$(CONFIG_CPU_AMD_GX1) += ../../../../src/cpu/amd/model_gx1/gx_setup.inc +crt0-$(CONFIG_MMX) += ../../../../src/cpu/x86/mmx/enable_mmx.inc +crt0-$(CONFIG_SSE) += ../../../../src/cpu/x86/sse/enable_sse.inc +crt0-y += failover.inc crt0-y += auto.inc -crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc -endif +crt0-$(CONFIG_SSE) += ../../../../src/cpu/x86/sse/disable_sse.inc +crt0-$(CONFIG_MMX) += ../../../../src/cpu/x86/mmx/disable_mmx.inc ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds |