diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2018-03-26 02:24:18 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-03-28 22:52:38 +0000 |
| commit | f5116952bb77ac361ad541dea00d9df28067219e (patch) | |
| tree | 16ef5146141c8cd340d6f67605234870f36c89d6 /src/mainboard | |
| parent | 8b76605a4af9b45894c39cd7b9c480bd96f523cd (diff) | |
| download | coreboot-f5116952bb77ac361ad541dea00d9df28067219e.tar.xz | |
soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
11 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index f8c3054012..2f077539a9 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 2e62f41fbb..f24d5c9cea 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a9646ec6cb..9d120ea9cf 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -67,7 +67,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 0dff3d95dd..94d9e53eb2 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 074e8a2a4c..032c42634a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 0b3387e2de..a04dd95e8d 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6946b38f14..8a946823fa 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 65955eb7d9..2688d58148 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7903ddcd39..6da73dc412 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -170,7 +170,6 @@ chip soc/intel/skylake # USB related register "SsicPortEnable" = "1" - register "XdciEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 50e484b0df..b3c5ffb51d 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index a52e4b7e3f..bf57398e9a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" |