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| author | Martin Roth <martinroth@google.com> | 2017-06-24 14:45:48 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-08 19:01:19 +0000 |
| commit | 77a58b92e8d44d17b9aa06710ed728a697722b4a (patch) | |
| tree | cd934fee0c39aa741bbad7112375877e3b05e9e8 /src/northbridge/amd/agesa/family15 | |
| parent | 3c35ad90534d4aebd6d9723e4614efb6af01f45c (diff) | |
| download | coreboot-77a58b92e8d44d17b9aa06710ed728a697722b4a.tar.xz | |
nb/amd: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15')
| -rw-r--r-- | src/northbridge/amd/agesa/family15/northbridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 15af02401a..cef6674f5c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -391,7 +391,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_ADAPTERS +#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS) extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); @@ -640,7 +640,7 @@ static void domain_enable_resources(device_t dev) /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); -#if CONFIG_AMD_SB_CIMX +#if IS_ENABLED(CONFIG_AMD_SB_CIMX) sb_After_Pci_Init(); #endif /* Enable MMIO on AMD CPU Address Map Controller */ @@ -1021,7 +1021,7 @@ static void cpu_bus_scan(device_t dev) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); } -#if CONFIG_CPU_AMD_SOCKET_G34 +#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34) u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); #else u32 apic_id = (i * core_max) + j + lapicid_start; |