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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 11:03:13 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:49:09 +0100 |
| commit | 59e03342076ea79cb7c0ed2fdbd199947c8c5212 (patch) | |
| tree | ec951913b7ad95c35faced30b4dadc6413619b5d /src/northbridge/amd/agesa/family15tn/northbridge.c | |
| parent | 7d09cfcf749c1c0fd1c3791585065b39ec1a3433 (diff) | |
| download | coreboot-59e03342076ea79cb7c0ed2fdbd199947c8c5212.tar.xz | |
AGESA: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn/northbridge.c')
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index ae1efb4db7..2353126049 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -325,13 +325,11 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) |