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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-06 19:02:56 +0300
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-08-27 15:35:34 +0200
commitcd9fc1aa5f483818385c4a6c98afee4c8f49ad8e (patch)
treef667f21df51ab25c76e065128247d65c50552262 /src/northbridge/amd/agesa/family15tn
parent8c0279088266beccdc8953ecf2dd340fa27ed768 (diff)
downloadcoreboot-cd9fc1aa5f483818385c4a6c98afee4c8f49ad8e.tar.xz
AMD northbridges: rewrite CPU allocation
Use of alloc_find_dev() prevents creation of a device duplicates for device_path and is SMP safe. Reduce scope of variables to make the code more readable and in preparation for refactoring the allocation out of northbridge.c. Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1186 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn')
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c41
1 files changed, 17 insertions, 24 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index fb30277884..6fc9434937 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -996,8 +996,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
/* Find which cpus are present */
cpu_bus = dev->link_list;
for (i = 0; i < node_nums; i++) {
- device_t cdb_dev, cpu;
- struct device_path cpu_path;
+ device_t cdb_dev;
unsigned busn, devn;
struct bus *pbus;
@@ -1053,6 +1052,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
} else {
siblings = 0; //default one core
}
+ int enable_node = cdb_dev && cdb_dev->enabled;
printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
@@ -1060,6 +1060,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
u32 lapicid_start = 0;
+ struct device_path cpu_path;
+ device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
@@ -1088,28 +1090,19 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, cpu_path.apic.apic_id);
- /* See if I can find the cpu */
- cpu = find_dev_path(cpu_bus, &cpu_path);
- /* Enable the cpu if I have the processor */
- if (cdb_dev && cdb_dev->enabled) {
- if (!cpu) {
- cpu = alloc_dev(cpu_bus, &cpu_path);
- }
- if (cpu) {
- cpu->enabled = 1;
- }
- }
- /* Disable the cpu if I don't have the processor */
- if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
- cpu->enabled = 0;
- }
- /* Report what I have done */
- if (cpu) {
- cpu->path.apic.node_id = i;
- cpu->path.apic.core_id = j;
- printk(BIOS_DEBUG, "CPU: %s %s\n",
- dev_path(cpu), cpu->enabled?"enabled":"disabled");
- }
+ /* Update CPU in devicetree. */
+ if (enable_node)
+ cpu = alloc_find_dev(cpu_bus, &cpu_path);
+ else
+ cpu = find_dev_path(cpu_bus, &cpu_path);
+ if (!cpu)
+ continue;
+
+ cpu->enabled = enable_node;
+ cpu->path.apic.node_id = i;
+ cpu->path.apic.core_id = j;
+ printk(BIOS_DEBUG, "CPU: %s %s\n",
+ dev_path(cpu), cpu->enabled?"enabled":"disabled");
} //j
}
return max;