summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/agesa/family16kb
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-03-17 06:42:54 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-06-10 05:48:37 +0200
commitfcbebb61c59e2af7aacc03a6215650a0369d4c69 (patch)
tree6f4a202882d15f5f0965457452d37df3a4e01edf /src/northbridge/amd/agesa/family16kb
parent58e26c74e085d6a52d26ec950f1aaf711c3ef0b1 (diff)
downloadcoreboot-fcbebb61c59e2af7aacc03a6215650a0369d4c69.tar.xz
PCI subsystem: Drop PCI_64BIT_PREF_MEM option
No board in the tree selects this and it looks like the implementation was done at chipset level while it should be part of PCI subsystem. When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test. Feature of placing prefetchable PCI memory above 4GB may not work if there is any 32-bit only prefetchable PCI BARs in the system. Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/agesa/family16kb')
-rw-r--r--src/northbridge/amd/agesa/family16kb/northbridge.c77
1 files changed, 0 insertions, 77 deletions
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 25f40b8c85..275ed3d6fa 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -666,30 +666,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
-
-#else
- struct bus *link;
- struct resource *resource;
- for (link=dev->link_list; link; link = link->next) {
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0|(link->link_num<<2));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
-
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2|(link->link_num<<2));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- }
-#endif
}
static void domain_enable_resources(device_t dev)
@@ -792,10 +769,6 @@ static void setup_uma_memory(void)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM
- struct resource *io, *mem1, *mem2;
- struct resource *res;
-#endif
unsigned long mmio_basek;
u32 pci_tolm;
u64 ramtop = 0;
@@ -806,56 +779,6 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM
-
- for (link = dev->link_list; link; link = link->next) {
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1|(link->link_num<<2));
- mem2 = find_resource(dev, 2|(link->link_num<<2));
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
-
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = tmp;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
- }
-
- for (res = &dev->resource_list; res; res = res->next)
- {
- res->flags |= IORESOURCE_ASSIGNED;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, "");
- }
-#endif
-
pci_tolm = 0xffffffffUL;
for (link = dev->link_list; link; link = link->next) {
pci_tolm = find_pci_tolm(link);