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authorPatrick Georgi <pgeorgi@chromium.org>2017-01-28 15:26:43 +0100
committerPatrick Georgi <pgeorgi@google.com>2017-02-10 18:04:11 +0100
commit2e08b59cdcf9a26ae9e6d4107be8e45a5fb9dbdf (patch)
tree243c5faab07837153940f6c208f39e665886f342 /src/northbridge/amd/agesa
parentded1e05d11675d899e07906e04032b3cc2f29711 (diff)
downloadcoreboot-2e08b59cdcf9a26ae9e6d4107be8e45a5fb9dbdf.tar.xz
ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()
Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd/agesa')
-rw-r--r--src/northbridge/amd/agesa/def_callouts.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c
index a2e12a9022..953774af31 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/northbridge/amd/agesa/def_callouts.c
@@ -143,7 +143,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
return AGESA_UNSUPPORTED;
/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
- if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0)
+ if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0)
die("No SPD data\n");
Status = AGESA_SUCCESS;