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authorStefan Reinauer <reinauer@chromium.org>2013-02-12 14:17:15 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-14 02:00:10 +0100
commit4aff4458f58398f54c248604694c7005294c1747 (patch)
treeeb3d9259255abc486a4d6d9eb53199b4d408053e /src/northbridge/amd/agesa
parentdc8259ce1d2e866f3133da49c1d6f4773f5698c1 (diff)
downloadcoreboot-4aff4458f58398f54c248604694c7005294c1747.tar.xz
sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa')
-rw-r--r--src/northbridge/amd/agesa/family10/northbridge.c6
-rw-r--r--src/northbridge/amd/agesa/family12/northbridge.c2
-rw-r--r--src/northbridge/amd/agesa/family14/northbridge.c4
-rw-r--r--src/northbridge/amd/agesa/family15/northbridge.c8
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c8
5 files changed, 14 insertions, 14 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index c5d570a3e7..59a12f174f 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -1244,7 +1244,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
@@ -1260,7 +1260,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
@@ -1446,7 +1446,7 @@ static void root_complex_enable_dev(struct device *dev)
}
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 9c598e85a1..e860594b66 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -921,7 +921,7 @@ static void root_complex_enable_dev(struct device *dev)
}
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 3d0b97f608..d955bcf666 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -345,7 +345,7 @@ static void nb_read_resources(device_t dev)
}
/*
- * This MMCONF resource must be reserved in the PCI_DOMAIN.
+ * This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
@@ -908,7 +908,7 @@ static void root_complex_enable_dev(struct device *dev)
}
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 1ac7e616f6..769d473c85 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -343,7 +343,7 @@ static void nb_read_resources(device_t dev)
}
/*
- * This MMCONF resource must be reserved in the PCI_DOMAIN.
+ * This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
@@ -938,7 +938,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
@@ -953,7 +953,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
@@ -1143,7 +1143,7 @@ static void root_complex_enable_dev(struct device *dev)
}
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 2ff5c1a9b5..41c2d8e506 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -339,7 +339,7 @@ static void nb_read_resources(device_t dev)
}
/*
- * This MMCONF resource must be reserved in the PCI_DOMAIN.
+ * This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
@@ -922,7 +922,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
@@ -937,7 +937,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (dev_mc && dev_mc->bus) {
printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
pci_domain = dev_mc->bus->dev;
- if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+ if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
@@ -1123,7 +1123,7 @@ static void root_complex_enable_dev(struct device *dev)
}
/* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;