AMD/agesa: Add functions for AMD PCI IRQ routing

Port the changes that were made in amd/cimx to amd/agesa
as were done in:
   commit c93a75a5ab067f86104028b74d92fc54cb939cd5
   Author: Mike Loptien <mike.loptien@se-eng.com>
   Date:   Fri Jun 6 15:16:29 2014 -0600

      AMD/CIMx: Add functions for AMD PCI IRQ routing

This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.

Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

2 files changed, 98 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h
new file mode 100644
index 0000000000..d0acb5ce43
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AMD_FAM15TN_PCI_DEVS_H_
+#define _AMD_FAM15TN_PCI_DEVS_H_
+
+#define BUS0 0
+
+/* Graphics and Display */
+#define GFX_DEV 0x1
+#define GFX_FUNC 0
+#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC)
+
+/* PCIe Ports */
+#define NB_PCIE_PORT1_DEV 0x2
+#define NB_PCIE_PORT2_DEV 0x3
+#define NB_PCIE_PORT3_DEV 0x4
+#define NB_PCIE_PORT4_DEV 0x5
+#define NB_PCIE_PORT5_DEV 0x6
+#define NB_PCIE_PORT6_DEV 0x7
+#define NB_PCIE_PORT7_DEV 0x8
+#define NB_PCIE_FUNC 0
+#define NB_PCIE_PORT1_DEVID 0x1412
+#define NB_PCIE_PORT2_DEVID 0x1413
+#define NB_PCIE_PORT3_DEVID 0x1414
+#define NB_PCIE_PORT4_DEVID 0x1415
+#define NB_PCIE_PORT5_DEVID 0x1416
+#define NB_PCIE_PORT6_DEVID 0x1417
+#define NB_PCIE_PORT7_DEVID 0x1418
+#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_PCIE_PORT6_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_PCIE_PORT7_DEV,NB_PCIE_FUNC)
+
+#endif /* _AMD_FAM15TN_PCI_DEVS_H_ */
diff --git a/src/northbridge/amd/agesa/family16kb/pci_devs.h b/src/northbridge/amd/agesa/family16kb/pci_devs.h
new file mode 100644
index 0000000000..be0f524139
--- /dev/null
+++ b/src/northbridge/amd/agesa/family16kb/pci_devs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AMD_FAM16KB_PCI_DEVS_H_
+#define _AMD_FAM16KB_PCI_DEVS_H_
+
+#define BUS0 0
+
+/* Graphics and Display */
+#define GFX_DEV 0x1
+#define GFX_FUNC 0
+#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC)
+
+/* PCIe Ports */
+#define NB_PCIE_PORT1_DEV 0x1
+#define NB_PCIE_PORT2_DEV 0x2
+#define NB_PCIE_PORT3_DEV 0x3
+#define NB_PCIE_PORT4_DEV 0x4
+#define NB_PCIE_PORT5_DEV 0x5
+#define NB_PCIE_FUNC 2
+#define NB_PCIE_PORT_DEVID 0x1439
+#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV,NB_PCIE_FUNC)
+#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV,NB_PCIE_FUNC)
+
+#endif /* _AMD_FAM16KB_PCI_DEVS_H_ */