Persimmon/Fam14/SB800 DSDT: Split into common areas

Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory.  Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future.  I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time.  Removing
it until it is decided that it is actually necessary.

This change was verified in three different ways:
	1. Visual comparison of the compiled DSDT pulled from the
	Persimmon after booting into Linux using the ACPI tools
	acpidump, acpixtract, and iasl.  The comparison was done
	between the DSDT before and after doing the split work.

	This test is somewhat difficult considering the expanse
	of the changes.  Blocks of code have been moved, and
	others changed.

	2. Linux logs were dumped before and after the DSDT split.
	Logs dumped and compared include dmesg and lspci -tv.
	Neither log changed significantly between the two compare
	points.

	3. The test suite FWTS was run on the Coreboot build both
	before and after doing the DSDT split with the command
	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
	-P specifies all power tests, and -u specifies utilities.
	Interactive jobs were not run as most of them consist of
	laptop checks.  Again, there were no significant changes
	between the two endpoints.

These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.

This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)

Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>

1 files changed, 130 insertions, 0 deletions

diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl
new file mode 100644
index 0000000000..24417066ef
--- /dev/null
+++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
+Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+Device(AMRT) {
+	Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* The internal GFX bridge */
+Device(AGPB) {
+	Name(_ADR, 0x00010000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APR1) }	/* APIC mode */
+		Return (PR1)				/* PIC Mode */
+	}
+}  /* end AGPB */
+
+/* The internal GFX bridge */
+Device(HDMI) {
+	Name(_ADR, 0x00010001)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APR1) }	/* APIC mode */
+		Return (PR1)				/* PIC Mode */
+	}
+}  /* end HDMI */
+
+/* Dev 2 & 3 are external GFX bridges, not used in Family14 */
+
+/* Dev4 GPP0 Root Port Bridge */
+Device(PBR4) {
+	Name(_ADR, 0x00040000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS4) }	/* APIC mode */
+		Return (PS4)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR4 */
+
+/* Dev5 GPP1 Root Port Bridge */
+Device(PBR5) {
+	Name(_ADR, 0x00050000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS5) }	/* APIC mode */
+		Return (PS5)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR5 */
+
+/* Dev6 GPP2 Root Port Bridge */
+Device(PBR6) {
+	Name(_ADR, 0x00060000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS6) }	/* APIC mode */
+		Return (PS6)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR6 */
+
+/* The onboard EtherNet chip */
+Device(PBR7) {
+	Name(_ADR, 0x00070000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS7) }	/* APIC mode */
+		Return (PS7)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR7 */
+
+Device(PE20) {
+	Name(_ADR, 0x00150000)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APE0) }	/* APIC mode */
+		Return (PE0)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PE20 */
+
+Device(PE21) {
+	Name(_ADR, 0x00150001)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APE1) }	/* APIC mode */
+		Return (PE1)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PE21 */
+
+Device(PE22) {
+	Name(_ADR, 0x00150002)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APE2) }	/* APIC mode */
+		Return (APE2)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PE22 */
+
+Device(PE23) {
+	Name(_ADR, 0x00150003)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APE3) }	/* APIC mode */
+		Return (PE3)				/* PIC Mode */
+	} /* end _PRT */
+} /* end PE23 */
+
+