diff options
author | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:32:08 +0000 |
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committer | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:32:08 +0000 |
commit | 8ae8c8822068ef1722c08073ffa4ecc25633cbee (patch) | |
tree | 8c7bbf2f7b791081e486439a9b7ffb2fd6e649ac /src/northbridge/amd/amdfam10/Config.lb | |
parent | 2006b38fed2f5f3680de1736f7fc878823f2f93b (diff) | |
download | coreboot-8ae8c8822068ef1722c08073ffa4ecc25633cbee.tar.xz |
Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/Config.lb')
-rw-r--r-- | src/northbridge/amd/amdfam10/Config.lb | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb new file mode 100644 index 0000000000..96619b23c6 --- /dev/null +++ b/src/northbridge/amd/amdfam10/Config.lb @@ -0,0 +1,79 @@ +# +# This file is part of the LinuxBIOS project. +# +# Copyright (C) 2007 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +uses CONFIG_CHIP_NAME +uses AGP_APERTURE_SIZE +uses HAVE_ACPI_TABLES + +default AGP_APERTURE_SIZE=0x4000000 + +if CONFIG_CHIP_NAME + config chip.h +end + +object northbridge.o +driver misc_control.o + +if HAVE_ACPI_TABLES + object amdfam10_acpi.o + makerule ssdt.c + depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" + action "mv ssdt.hex ssdt.c" + end + object ./ssdt.o + makerule sspr1.c + depends "$(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex" + action "mv sspr1.hex sspr1.c" + end + object ./sspr1.o + makerule sspr2.c + depends "$(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex" + action "mv sspr2.hex sspr2.c" + end + object ./sspr2.o + makerule sspr3.c + depends "$(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex" + action "mv sspr3.hex sspr3.c" + end + object ./sspr3.o + makerule sspr4.c + depends "$(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex" + action "mv sspr4.hex sspr4.c" + end + object ./sspr4.o + makerule sspr5.c + depends "$(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" + action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" + action "perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex" + action "mv sspr5.hex sspr5.c" + end + object ./sspr5.o +end + +object get_pci1234.o |