amdfam10: Perform major include ".c" cleanup

Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>

1 files changed, 26 insertions, 26 deletions

diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h
index c1ef29ecee..2f9c7bafd6 100644
--- a/src/northbridge/amd/amdfam10/raminit.h
+++ b/src/northbridge/amd/amdfam10/raminit.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,31 +13,31 @@
  * GNU General Public License for more details.
  */
 
-#ifndef RAMINIT_H
-#define RAMINIT_H
+#ifndef AMDFAM10_RAMINIT_H
+#define AMDFAM10_RAMINIT_H
 
-//DDR2 REG and unbuffered : Socket F 1027 and AM3
-/* every channel have 4 DDR2 DIMM for socket F
- *		       2 for socket M2/M3
- *		       1 for socket s1g1
- */
-#define DIMM_SOCKETS 4
-struct mem_controller {
-	u32 node_id;
-	pci_devfn_t f0, f1, f2, f3, f4, f5;
-	/* channel0 is DCT0 --- channelA
-	 * channel1 is DCT1 --- channelB
-	 * can be ganged, a single dual-channel DCT ---> 128 bit
-	 *	 or unganged a two single-channel DCTs ---> 64bit
-	 * When the DCTs are ganged, the writes to DCT1 set of registers
-	 * (F2x1XX) are ignored and reads return all 0's
-	 * The exception is the DCT phy registers, F2x[1,0]98, F2x[1,0]9C,
-	 * and all the associated indexed registers, are still
-	 * independently accessiable
-	 */
-	/* FIXME: I will only support ganged mode for easy support */
-	u8 spd_switch_addr;
-	u8 spd_addr[DIMM_SOCKETS*2];
-};
+#include <device/pci.h>
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <northbridge/amd/amdmct/wrappers/mcti.h>
+
+struct sys_info;
+struct DCTStatStruc;
+struct MCTStatStruc;
+
+int mctRead_SPD(u32 smaddr, u32 reg);
+void mctSMBhub_Init(u32 node);
+void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
+void raminit_amdmct(struct sys_info *sysinfo);
+void amdmct_cbmem_store_info(struct sys_info *sysinfo);
+void fill_mem_ctrl(u32 controllers, struct mem_controller *ctrl_a, const u8 *spd_addr);
+uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq);
+u8 mctGetProcessorPackageType(void);
+void Set_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg, uint32_t val);
+uint32_t Get_NB32_DCT(uint32_t dev, uint8_t dct, uint32_t reg);
+uint32_t Get_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index);
+void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data);
+void fam15h_switch_dct(uint32_t dev, uint8_t dct);
+uint32_t Get_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg);
+void Set_NB32_DCT_NBPstate(uint32_t dev, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t val);
 
 #endif