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| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/northbridge/amd/amdfam10/reset_test.c | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
| download | coreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/reset_test.c')
| -rw-r--r-- | src/northbridge/amd/amdfam10/reset_test.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 389d8e60a9..69869bf48c 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -43,7 +43,7 @@ static u32 cpu_init_detected(u8 nodeid) static u32 bios_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -51,7 +51,7 @@ static u32 bios_reset_detected(void) static u32 cold_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -59,7 +59,7 @@ static u32 cold_reset_detected(void) static u32 other_reset_detected(void) // other warm reset not started by BIOS { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); } @@ -91,7 +91,7 @@ static void set_bios_reset(void) device_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; for(i = 0; i < nodes; i++) { dev = NODE_PCI(i,0); @@ -115,7 +115,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b for(reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -126,7 +126,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b } } -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // let's check that in extend space // use the nodeid extend space to find out the bus for the linkn u32 tempreg; @@ -157,8 +157,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b static u32 get_sblk(void) { u32 reg; - /* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64); + /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); return ((reg>>8) & 3) ; } |