diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-02-28 20:10:20 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2009-02-28 20:10:20 +0000 |
commit | 2b34db8d1de2d63ffa829fe03db0ce2aaba40233 (patch) | |
tree | ba18eb28d25a5e5d28c3b8609b5a292982eed08c /src/northbridge/amd/amdfam10 | |
parent | 3c924d2f48ba1bb6a9d5a20453f230bb6be726e0 (diff) | |
download | coreboot-2b34db8d1de2d63ffa829fe03db0ce2aaba40233.tar.xz |
coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r-- | src/northbridge/amd/amdfam10/amdfam10_acpi.c | 10 | ||||
-rw-r--r-- | src/northbridge/amd/amdfam10/misc_control.c | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 20 |
3 files changed, 16 insertions, 16 deletions
diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c index b33ea488cf..52c438e7dd 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c +++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c @@ -41,7 +41,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) if (!cpu->enabled) { continue; } - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.apic.apic_id); cpu_index++; } return current; @@ -79,8 +79,8 @@ unsigned long acpi_create_srat_lapics(unsigned long current) if (!cpu->enabled) { continue; } - printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); - current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); + printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id); + current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id); cpu_index++; } return current; @@ -357,13 +357,13 @@ unsigned long acpi_add_ssdt_pstates(acpi_rsdt_t *rsdt, unsigned long current) if (!cpu->enabled) { continue; } - printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.core_id); + printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id); current = ( current + 0x0f) & -0x10; ssdt = (acpi_header_t *)current; current += ((acpi_header_t *)AmlCode_sspr)->length; memcpy((void *)ssdt, (void *)AmlCode_sspr, ((acpi_header_t *)AmlCode_sspr)->length); - update_sspr((void*)ssdt,cpu->path.u.apic.node_id, cpu_index); + update_sspr((void*)ssdt,cpu->path.apic.node_id, cpu_index); /* recalculate checksum */ ssdt->checksum = 0; ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 5fcee31cc8..634fec53ce 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -59,7 +59,7 @@ static void mcf3_read_resources(device_t dev) pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.u.pci.devfn != PCI_DEVFN(CDB, 3)) { + if (dev->path.pci.devfn != PCI_DEVFN(CDB, 3)) { return; } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e335ea7f1f..38b152c8e8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -114,13 +114,13 @@ static u32 amdfam10_nodeid(device_t dev) unsigned busn; busn = dev->bus->secondary; if(busn != CBB) { - return (dev->path.u.pci.devfn >> 3) - CDB + 32; + return (dev->path.pci.devfn >> 3) - CDB + 32; } else { - return (dev->path.u.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CDB; } #else - return (dev->path.u.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CDB; #endif } @@ -1289,7 +1289,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk_debug("%s\n",dev_path(dev_mc)); while(dev_mc){ printk_debug("%s move to ",dev_path(dev_mc)); - dev_mc->path.u.pci.devfn -= PCI_DEVFN(0x18,0); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); printk_debug("%s\n",dev_path(dev_mc)); dev_mc = dev_mc->sibling; } @@ -1395,7 +1395,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Build the cpu device path */ cpu_path.type = DEVICE_PATH_APIC; - cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? + cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? /* See if I can find the cpu */ cpu = find_dev_path(cpu_bus, &cpu_path); @@ -1417,16 +1417,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Report what I have done */ if (cpu) { - cpu->path.u.apic.node_id = i; - cpu->path.u.apic.core_id = j; + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { - cpu->path.u.apic.apic_id += sysconf.apicid_offset; + cpu->path.apic.apic_id += sysconf.apicid_offset; } else { - if (cpu->path.u.apic.apic_id != 0) - cpu->path.u.apic.apic_id += sysconf.apicid_offset; + if (cpu->path.apic.apic_id != 0) + cpu->path.apic.apic_id += sysconf.apicid_offset; } } #endif |