diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-09-05 17:55:58 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-10-26 23:52:54 +0100 |
| commit | b8a355dcdf319671b97f8688209ad5d471fc0905 (patch) | |
| tree | 6cd55b06343af460642431bb8dd3d782d0ccc45e /src/northbridge/amd/amdfam10 | |
| parent | 7a5413a81c2fecc443999b006d641cd903327346 (diff) | |
| download | coreboot-b8a355dcdf319671b97f8688209ad5d471fc0905.tar.xz | |
northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalization
The native AMD DDR3 memory initialization code was riddled with
numerous errors and was missing critical configuration code segments;
this made it so that DDR3 memory did not function on most AMD boards.
This patch corrects enough of the DDR3 initialization such that
UDIMMs can be used on most channels of G34 Opteron boards. Further
work is needed to fix the broken RDIMM code and remaining UDIMM issues.
Change-Id: Iab690db769e820600693ad1170085623b177b94e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11941
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdfam10')
| -rw-r--r-- | src/northbridge/amd/amdfam10/raminit_amdmct.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index a0d47f4afd..25cf93daf7 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -26,7 +26,6 @@ static void print_tx(const char *strval, u32 val) printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } -#endif static void print_t(const char *strval) { @@ -34,6 +33,7 @@ static void print_t(const char *strval) printk(BIOS_DEBUG, "%s", strval); #endif } +#endif static void print_tf(const char *func, const char *strval) { |