summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdfam10
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-06 22:07:58 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-08 17:21:09 +0200
commitba817d0931eb9bbf23d6c09f56f9ea2ba22fdad6 (patch)
tree0b0e0e086ba403de436a1f897aae9871bdc33d11 /src/northbridge/amd/amdfam10
parente9205d537ca92e0dfa882a76617e8e9fb664e108 (diff)
downloadcoreboot-ba817d0931eb9bbf23d6c09f56f9ea2ba22fdad6.tar.xz
nb/amd/mct_ddr3: Reenable sync flood after ECC init
The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14270 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index eee5c465fb..775af66b9d 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev)
/* Clear MC4 error status */
pci_write_config32(dev, 0x48, 0x0);
pci_write_config32(dev, 0x4c, 0x0);
-
- if (mem_info->dct_stat[node].mca_config_backed_up) {
- dword = pci_read_config32(dev, 0x44);
- dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30;
- dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21;
- dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
- pci_write_config32(dev, 0x44, dword);
- }
}
}
#endif