summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdfam10
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-09-05 18:56:05 -0500
committerMartin Roth <martinroth@google.com>2015-11-02 23:26:41 +0100
commit2a83935d9f50e3059e7747338a700c2fceb1731a (patch)
treeb40831293a339c6743ec86e7820111c38c536113 /src/northbridge/amd/amdfam10
parent65eec4d959a847c43b5f4e92c6eee60f042fd7f6 (diff)
downloadcoreboot-2a83935d9f50e3059e7747338a700c2fceb1731a.tar.xz
northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11957 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r--src/northbridge/amd/amdfam10/Kconfig4
-rw-r--r--src/northbridge/amd/amdfam10/acpi.c3
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c30
3 files changed, 35 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 3ea1e4643f..17968b4b90 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -83,6 +83,10 @@ config DIMM_REGISTERED
bool
default n
+config DIMM_VOLTAGE_SET_SUPPORT
+ bool
+ default n
+
if DIMM_FBDIMM
config DIMM_SUPPORT
hex
diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index 5ff38aab49..ad54abd765 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -303,8 +303,7 @@ void northbridge_acpi_write_vars(device_t device)
} else {
if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0
CBST = (u8) (0x0f);
- }
- else {
+ } else {
CBST = (u8) (0x00);
}
}
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 2846ed3015..2e7fc3a990 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1063,6 +1063,36 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle,
snprintf(string_buffer, sizeof (string_buffer), "%08X", mem_info->dct_stat[node].DimmSerialNumber[slot]);
t->serial_number = smbios_add_string(t->eos, string_buffer);
}
+ if (IS_ENABLED(CONFIG_DIMM_DDR2)) {
+ /* JEDEC specifies 1.8V only, so assume that the memory is configured for 1.8V */
+ t->minimum_voltage = 1800;
+ t->maximum_voltage = 1800;
+ t->configured_voltage = 1800;
+ } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
+#if IS_ENABLED(CONFIG_DIMM_DDR3)
+ /* Find the maximum and minimum supported voltages */
+ uint8_t supported_voltages = mem_info->dct_stat[node].DimmSupportedVoltages[slot];
+ if (supported_voltages & 0x8)
+ t->minimum_voltage = 1150;
+ else if (supported_voltages & 0x4)
+ t->minimum_voltage = 1250;
+ else if (supported_voltages & 0x2)
+ t->minimum_voltage = 1350;
+ else if (supported_voltages & 0x1)
+ t->minimum_voltage = 1500;
+
+ if (supported_voltages & 0x1)
+ t->maximum_voltage = 1500;
+ else if (supported_voltages & 0x2)
+ t->maximum_voltage = 1350;
+ else if (supported_voltages & 0x4)
+ t->maximum_voltage = 1250;
+ else if (supported_voltages & 0x8)
+ t->maximum_voltage = 1150;
+
+ t->configured_voltage = mem_info->dct_stat[node].DimmConfiguredVoltage[slot];
+#endif
+ }
t->memory_error_information_handle = 0xFFFE; /* no error information handle available */
single_len = t->length + smbios_string_table_len(t->eos);
len += single_len;