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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-12 10:54:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:51:26 +0000
commit400ce55566caa541304b2483e61bcc2df941998c (patch)
tree4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/amdfam10
parente64a585374de88ea896ed517445a34986aa321b9 (diff)
downloadcoreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/amdfam10')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index ff4f0a397a..4da5228666 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -28,7 +28,6 @@
#include <smbios.h>
#include <cpu/cpu.h>
#include <delay.h>
-
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
@@ -734,7 +733,7 @@ static void amdfam10_domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
/* We have MMCONF_SUPPORT, create the resource window. */
- mmconf_resource(dev, 0xc0010058);
+ mmconf_resource(dev, MMIO_CONF_BASE);
/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);