diff options
author | Damien Zammit <damien@zamaudio.com> | 2016-11-28 00:29:10 +1100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-01-04 18:56:01 +0100 |
commit | 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 (patch) | |
tree | 618c2bc04f44cf73d3dae288bff0a5e2ef44d616 /src/northbridge/amd/amdht | |
parent | 6c20b65849aeda664cc40ebc0f0bab2e99768423 (diff) | |
download | coreboot-75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7.tar.xz |
amdfam10: Perform major include ".c" cleanup
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Diffstat (limited to 'src/northbridge/amd/amdht')
-rw-r--r-- | src/northbridge/amd/amdht/Makefile.inc | 5 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/comlib.c | 7 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/comlib.h | 11 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/h3ffeat.h | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/h3finit.c | 20 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/h3finit.h | 2 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/h3ncmn.c | 27 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/h3ncmn.h | 30 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/ht_wrapper.c | 44 | ||||
-rw-r--r-- | src/northbridge/amd/amdht/ht_wrapper.h | 7 |
10 files changed, 70 insertions, 85 deletions
diff --git a/src/northbridge/amd/amdht/Makefile.inc b/src/northbridge/amd/amdht/Makefile.inc new file mode 100644 index 0000000000..0b33352e7c --- /dev/null +++ b/src/northbridge/amd/amdht/Makefile.inc @@ -0,0 +1,5 @@ +ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y) + +romstage-y += h3finit.c ht_wrapper.c comlib.c AsPsNb.c h3ncmn.c + +endif diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index 7a15325588..85cbbc4811 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -17,6 +17,13 @@ #define FILECODE 0xCCCC #include "comlib.h" +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + + /* *--------------------------------------------------------------------------- * EXPORTED FUNCTIONS diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index b696b695f3..d497fd28e4 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -16,16 +16,13 @@ #ifndef COMLIB_H #define COMLIB_H -#ifndef FILECODE -#error "FILECODE was not defined, should be #define'd to 0xFxxx" -#endif +#undef FILECODE +#define FILECODE 0xF001 +#include <inttypes.h> +#include <stdlib.h> #include "porting.h" -/* include coreboot pci functions */ -#include <device/pci_def.h> -#include <device/pci_ids.h> - #ifdef AMD_DEBUG #define ASSERT(x) ((x) ? 0 : ErrorStop(((uint32)FILECODE)*0x10000 + ((__LINE__)%10) + (((__LINE__/10)%10)*0x10) + (((__LINE__/100)%10)*0x100) +(((__LINE__/1000)%10)*0x1000))) #else diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index bcd4c10cd2..59e8feba47 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -18,6 +18,8 @@ #ifndef H3FFEAT_H #define H3FFEAT_H +#include "h3finit.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 2baf886c31..6a9d8983af 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -21,19 +21,20 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xF001 - -#include "comlib.h" #include "h3finit.h" #include "h3ffeat.h" #include "h3ncmn.h" #include "h3gtopo.h" #include "AsPsNb.h" -/* this is pre-ram so include the required C files here */ -#include "comlib.c" -#include "AsPsNb.c" -#include "h3ncmn.c" + +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS @@ -41,9 +42,6 @@ *---------------------------------------------------------------------------- */ -#undef FILECODE -#define FILECODE 0xF001 - /* APIC defines from amdgesa.inc, which can't be included in to c code. */ #define APIC_Base_BSP 8 #define APIC_Base 0x1b diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index c9737929a1..45ed3c180c 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -17,6 +17,8 @@ #ifndef H3FINIT_H #define H3FINIT_H +#include "comlib.h" + /*---------------------------------------------------------------------------- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) * diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 0d0055b4f6..5f656f5e32 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -23,11 +23,19 @@ #undef FILECODE #define FILECODE 0xF002 +#include "h3ncmn.h" #include "h3finit.h" #include "h3ffeat.h" -#include "h3ncmn.h" #include "AsPsNb.h" +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> + /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS @@ -89,22 +97,7 @@ *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS *** ***************************************************************************/ -static inline uint8_t is_fam15h(void) -{ - uint8_t fam15h = 0; - uint32_t family; - - family = cpuid_eax(0x80000001); - family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); - - if (family >= 0x6f) - /* Family 15h or later */ - fam15h = 1; - - return fam15h; -} - -static inline uint8_t is_gt_rev_d(void) +inline uint8_t is_gt_rev_d(void) { uint8_t fam15h = 0; uint8_t rev_gte_d = 0; diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 3c8a34612f..f4a782d63b 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -17,17 +17,13 @@ #ifndef H3NCMN_H #define H3NCMN_H -/*---------------------------------------------------------------------------- - * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) - * - *---------------------------------------------------------------------------- - */ - -/*----------------------------------------------------------------------------- - * DEFINITIONS AND MACROS - * - *----------------------------------------------------------------------------- - */ +#include <inttypes.h> +#include <device/pci.h> +#include <console/console.h> +#include <cpu/amd/msr.h> +#include "comlib.h" +#include "h3finit.h" +#include "h3ffeat.h" /* Use a macro to convert a node number to a PCI device. If some future port of * this code needs to, this can easily be replaced by a function call: @@ -65,12 +61,6 @@ ((u16)fc & HT_FREQUENCY_LIMIT_HT1_ONLY) #endif -/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS - * - *---------------------------------------------------------------------------- - */ - struct cNorthBridge { /* Public data, clients of northbridge can access */ @@ -119,11 +109,7 @@ struct cNorthBridge u32 compatibleKey; } ; -/*---------------------------------------------------------------------------- - * FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ void newNorthBridge(u8 node, cNorthBridge *nb); +uint8_t is_gt_rev_d(void); #endif /* H3NCMN_H */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 4c68f41337..8a25993646 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -16,8 +16,6 @@ #include <cpu/x86/msr.h> #include <console/console.h> -#include <northbridge/amd/amdfam10/amdfam10.h> - #include "ht_wrapper.h" /*---------------------------------------------------------------------------- @@ -51,37 +49,12 @@ #include "h3gtopo.h" #include "h3finit.h" -/* include the main HT source file */ -#include "h3finit.c" - - /*---------------------------------------------------------------------------- * LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */ -/* FIXME: Find a better place for these pre-ram functions. */ -#define NODE_HT(x) NODE_PCI(x,0) -#define NODE_MP(x) NODE_PCI(x,1) -#define NODE_MC(x) NODE_PCI(x,3) -#define NODE_LC(x) NODE_PCI(x,4) - -static u32 get_nodes(void) -{ - pci_devfn_t dev; - u32 nodes; - - dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); -#if CONFIG_MAX_PHYSICAL_CPUS > 8 - nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); -#endif - nodes++; - - return nodes; -} - static const char * event_class_string_decodes[] = { [HT_EVENT_CLASS_CRITICAL] = "CRITICAL", [HT_EVENT_CLASS_ERROR] = "ERROR", @@ -255,7 +228,7 @@ static BOOL AMD_CB_IgnoreLink (u8 node, u8 link) * AMD HT init coreboot wrapper * */ -static void amd_ht_init(struct sys_info *sysinfo) +void amd_ht_init(struct sys_info *sysinfo) { if (!sysinfo) { @@ -390,3 +363,18 @@ void amd_ht_fixup(struct sys_info *sysinfo) { } } } + +u32 get_nodes(void) +{ + pci_devfn_t dev; + u32 nodes; + + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7); +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); +#endif + nodes++; + + return nodes; +} diff --git a/src/northbridge/amd/amdht/ht_wrapper.h b/src/northbridge/amd/amdht/ht_wrapper.h index 5c3c2d9a9d..331c3df5f3 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.h +++ b/src/northbridge/amd/amdht/ht_wrapper.h @@ -16,6 +16,13 @@ #ifndef AMD_HT_WRAPPER_H #define AMD_HT_WRAPPER_H +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <inttypes.h> +#include "h3finit.h" + void amd_ht_fixup(struct sys_info *sysinfo); +u32 get_nodes(void); +void amd_ht_init(struct sys_info *sysinfo); #endif |