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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/amdht | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/amdht')
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index d4e6a29f42..7e6a63d857 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -21,19 +21,6 @@ #define APIC_BAR 0x1b /* APIC_BAR register */ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ -#define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */ -#define PS_MAX_VAL_SHFT 4 /* P-state Maximum Value shift position */ - -#define PS_CTL_REG 0xC0010062 /* P-state Control Register */ -#define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */ - -#define PS_STS_REG 0xC0010063 /* P-state Status Register */ -#define PS_STS_MASK 0x7 /* P-state Status Mask */ - -#define PS_REG_BASE 0xC0010064 /* P-state Register base */ -#define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */ -#define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */ - /* P-state register offset */ #define PS_REG0 0 /* offset for P0 */ #define PS_REG1 1 /* offset for P1 */ @@ -286,7 +273,6 @@ #define TSC_MSR 0x10 -#define CUR_PSTATE_MSR 0xc0010063 #define TSC_FREQ_SEL_SHIFT 24 #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) |